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Author SHA1 Message Date
Bradley Smith
cb9ca905e3 [ARM64] Flag setting logical/add/sub immediate instructions don't use SP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205895 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:44 +00:00
Bradley Smith
19b573d9c9 [ARM64] Conditional branches must always print their condition code, even AL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205894 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:39 +00:00
Bradley Smith
42c672649c [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205893 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:36 +00:00
Bradley Smith
6a82fbc29f [ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205892 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:31 +00:00
Bradley Smith
ae30bea9d7 [ARM64] Add missing shifted register MVN alias to ORN 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205891 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:26 +00:00
Bradley Smith
7face75878 [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205890 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:22 +00:00
Bradley Smith
7b5940c0c0 [ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a dumb alias. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205889 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:18 +00:00
Bradley Smith
250f973d7f [ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all labels types 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205888 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:12 +00:00
Bradley Smith
9a9fa81c1a [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205887 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:07 +00:00
Bradley Smith
86c067813c [ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205886 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:03 +00:00
Bradley Smith
5a09ce9ad1 [ARM64] Rename LR to the UAL-compliant 'X30'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205885 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:59 +00:00
Bradley Smith
37fe6627f6 [ARM64] Rename FP to the UAL-compliant 'X29'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205884 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:50 +00:00
Bradley Smith
6af2db2222 [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be zero but should be decoded/disassembled with any value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205883 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:40 +00:00
Bradley Smith
f797751ca0 [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205882 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:35 +00:00
Bradley Smith
5c73bde178 [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top bit of their immediate clear. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205881 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:31 +00:00
Bradley Smith
90c8a50b62 [ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205880 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:27 +00:00
Bradley Smith
98422af96f [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205879 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:24 +00:00
Bradley Smith
47c311bafe [ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205878 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:20 +00:00
Bradley Smith
8acef8d96d [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205877 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:15 +00:00
Bradley Smith
a8f8d292ca [ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205876 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:11 +00:00
Bradley Smith
3d41487f0e [ARM64] Rework system register parsing to overcome SPSel clash in MSR variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205875 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:06 +00:00
Bradley Smith
436fe613fc [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205874 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:01 +00:00
Bradley Smith
dcb9231b8a [ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disassembly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205873 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:56 +00:00
Bradley Smith
84998a1fa9 [ARM64] Remove PrefetchOp and use ARM64PRFM instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205872 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:53 +00:00
Bradley Smith
4be472c874 [ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205871 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:49 +00:00
Bradley Smith
b336e5d041 [ARM64] Remove ARM64SYS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205870 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:45 +00:00
Bradley Smith
96e05ca4bf [ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205869 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:42 +00:00
Bradley Smith
fb7edfa9a5 [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205868 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:36 +00:00
Bradley Smith
01229fa891 [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205867 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:27 +00:00
Bradley Smith
0fc7d2bdd2 [ARM64] Copy the named immediate operand mapping logic and enums from AArch64. AArch64's named immediate mapping and parsing is much more advanced than ARM64's. No functionality change - they're currently living side by side while I switch uses over. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205866 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:16 +00:00
Bradley Smith
a493b7786a [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205865 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:11 +00:00
Bradley Smith
a5b549e03c [ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205864 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:07 +00:00
Bradley Smith
4580af747e [ARM64] Add missing 1Q -> 1q vector kind alias 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205863 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:01 +00:00
Bradley Smith
1ff9280e05 [ARM64] Add parsing for vector lists such as {v0.8b-v3.8b} 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205862 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:41:58 +00:00
Bradley Smith
f5234a2c6c [ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather than UXTX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205861 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:41:53 +00:00
Bradley Smith
35b8c724c7 [ARM64] STRHro and STRBro were not being decoded at all. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205860 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:41:49 +00:00
Bradley Smith
6307036c7c [ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205859 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:41:45 +00:00
Bradley Smith
7ac29214ce [ARM64] Register-offset loads and stores with the 'option' field equal to 00x or 10x are undefined. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205858 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:41:38 +00:00
Filipe Cabecinhas
c657a09ea6 Revert "YAMLIO: Encode ambiguous hex strings explicitly" 
This reverts commit r205839.

It broke several tests in lld.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205857 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:35:17 +00:00
Arnold Schwaighofer
b0ee2374ce SLPVectorizer: Only vectorize intrinsics whose operands are widened equally 
The vectorizer only knows how to vectorize intrinics by widening all operands by
the same factor.

Patch by Tyler Nowicki!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205855 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:20:47 +00:00
Elena Demikhovsky
0d5d656524 AVX-512: insert element to mask vector; store i1 data 
Implemented INSERT_VECTOR_ELT operation for v16i1 and v8i1 vectors;
Implemented "store" for i1 type


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205850 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 12:37:50 +00:00
Viktor Kutuzov
d97cbff528 Add support for building LLVM on FreeBSD 9.2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205847 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 11:43:34 +00:00
Daniel Sanders
e777fb4725 Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable-no-nans-fp-math 
Summary:
They behave in accordance with the Has2008 and ABS2008 configuration bits of the processor which are used to select between the 1985 and 2008 versions of IEEE 754. In 1985 mode, these instructions are arithmetic (i.e. they raise invalid operation exceptions when given NaN), in 2008 mode they are non-arithmetic (i.e. they are copies).

nmadd.[ds], and nmsub.[ds] are still subject to -enable-no-nans-fp-math because the ISA spec does not explicitly state that they obey Has2008 and ABS2008.

Fixed the issue with the previous version of this patch (r205628). A pre-existing 'let Predicate =' statement was removing some predicates that were necessary for FP64 to behave correctly.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3274



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205844 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 09:56:43 +00:00
David Majnemer
7184f49f40 YAMLIO: Encode ambiguous hex strings explicitly 
YAMLIO would turn a BinaryRef into the string 0000000004000000.
However, the leading zero causes parsers to interpret it as being an
octal number instead of a hexadecimal one.

Instead, escape such strings as needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205839 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 07:56:27 +00:00
Tobias Grosser
144ffd6624 Delinearize: Extend informationin -analyze output 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205838 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 07:53:49 +00:00
Matt Arsenault
d4786ed1de R600/SI: Match not instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205837 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 07:16:16 +00:00
Tim Northover
87a79507fa ARM64: scalarize v1i64 mul operation 
This is the second part of fixing PR19367.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205836 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 07:07:02 +00:00
Tim Northover
7db3c63bb2 ARM64: add pattern for <1 x i64> custom not node. 
This should fix PR19367.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205835 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 06:55:39 +00:00
Saleem Abdulrasool
d640febcc8 Object: add type names for ARM/COFF relocations 
Add type name mappings for the ARM COFF relocations.  This allows for objdump to
provide a more useful description of relocations in disassembly inline form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205834 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 06:18:28 +00:00
Saleem Abdulrasool
e866d00e79 ARM MC: 80 column 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205833 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 06:18:26 +00:00