Commit Graph

2176 Commits

Author SHA1 Message Date
Johnny Chen
6341c5a4c4 Added the following 32-bit Thumb instructions for disassembly only: SMC, RFE,
and SRS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97164 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-25 20:25:24 +00:00
Johnny Chen
ce6275fd2c Added the 32-bit Thumb instructions (BXJ) for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97163 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-25 19:05:29 +00:00
Johnny Chen
2333655ed0 Added the 32-bit Thumb instructions (MRS and MSR) for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97159 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-25 18:46:43 +00:00
Johnny Chen
d86d269f08 Added the following 16-bit Thumb instructions for disassembly only: YIELD, WFE,
WFI, SEV, SETEND.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97149 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-25 17:51:03 +00:00
Johnny Chen
bd2c623903 Added tNOP for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97105 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-25 03:28:51 +00:00
Johnny Chen
4c61cdd307 Added tSVC and tTRAP for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-25 02:21:11 +00:00
Jakob Stoklund Olesen
657baec0af Create a stack frame on ARM when
- Function uses all scratch registers AND
- Function does not use any callee saved registers AND
- Stack size is too big to address with immediate offsets.

In this case a register must be scavenged to calculate the address of a stack
object, and the scavenger needs a spare register or emergency spill slot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97071 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-24 22:43:17 +00:00
Bob Wilson
e742bb53a3 Check for comparisons of +/- zero when optimizing less-than-or-equal and
greater-than-or-equal SELECT_CCs to NEON vmin/vmax instructions.  This is
only allowed when UnsafeFPMath is set or when at least one of the operands
is known to be nonzero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97065 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-24 22:15:53 +00:00
Johnny Chen
d88360495a Added Vector Swap (VSWPd and VSWPq) instructions for disassembly only.
A8.6.405


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97052 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-24 20:06:07 +00:00
Jakob Stoklund Olesen
9e6396d05e Stay away from str <undef> in ARMLoadStoreOpt. This pass does not understand
<undef> operands, and can cause scavenger failures when it translates
<kill,undef> to <kill>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97046 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-24 18:57:08 +00:00
Johnny Chen
39b03163a7 Fixed typo of opcodestr, should be "vst1", not "vld1".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97044 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-24 18:00:40 +00:00
Chandler Carruth
ff28103b19 Remove an unused variable. Was this intentional?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97022 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-24 06:09:03 +00:00
Johnny Chen
f50e83fd03 Added for disassembly VST1 (multiple single elements) which stores elements to
memory from three or four registers and VST2 (multiple two-element structures)
which stores to memory from two double-spaced registers.

A8.6.391 & A8.6.393


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-24 02:57:20 +00:00
Jim Grosbach
5f366af2ff handle very large call frames when require SPAdj != 0 for Thumb1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97013 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-24 02:15:43 +00:00
Jim Grosbach
f9a4b7653d LowerCall() should always do getCopyFromReg() to reference the stack pointer.
Machine instruction selection is much happier when operands are in virtual
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97012 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-24 01:43:03 +00:00
Johnny Chen
d7283d9c54 Added for disassembly VLD1 (multiple single elements) which loads memory into
three or four registers and VLD2 (multiple two-element structures) which loads
memory into two double-spaced registers.

A8.6.307 & A8.6.310


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-23 20:51:23 +00:00
Jim Grosbach
cf453ee70a Spelling. s/suppor /support /
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96954 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-23 17:16:27 +00:00
Johnny Chen
363ac58263 Added versions of VCGE, VCGT, VCLE, and VCLT NEON instructions which compare to
(immediate #0) for disassembly only.

A8.6.283, A8.6.285, A8.6.287, A8.6.290


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96856 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-23 01:42:58 +00:00
Johnny Chen
ec5a4cd14c Added VCEQ (immediate #0) NEON instruction for disassembly only.
A8.6.281


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96838 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-23 00:33:12 +00:00
Jim Grosbach
4642ad3af1 Updated version of r96634 (which was reverted due to failing 176.gcc and
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96822 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-22 23:10:38 +00:00
Jim Grosbach
5a0815fae8 Clean up a bit and fix for when SPAdj != 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96818 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-22 22:54:55 +00:00
Jim Grosbach
4c7628e43d The predicate index isn't fixed, so scan for it to make sure we get the proper
value.

Thumb2 uses the tADJCALLSTACK* instructions, and doesn't need t2 versions, so
remove the FIXME entry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96817 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-22 22:47:46 +00:00
Johnny Chen
2ec5e49a2b Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD,
for disassembly only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96806 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-22 21:50:40 +00:00
Johnny Chen
667d127b0b Added a bunch of instructions for disassembly only:
o signed/unsigned add/subtract
o signed/unsigned halving add/subtract
o unsigned sum of absolute difference [and accumulate]
o signed/unsigned saturate
o signed multiply accumulate/subtract [long] dual


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96795 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-22 18:50:54 +00:00
Johnny Chen
b92a23fcfc Undo r96654. The printing of ARM shift instructions in canonical forms can be
handled in ARMInstPrinter.cpp.

And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96719 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-21 04:42:01 +00:00
Bob Wilson
1a2e8686f8 Revert 96634. It causes assertion failures for 126.gcc and 176.gcc in
the armv6 nightly tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96691 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-19 18:59:53 +00:00
Johnny Chen
8f5e04098f Added entries for ASR, LSL, LSR, ROR, and RRX so that the disassembler prints
out the canonical form (A8.6.98) instead of the pseudo-instruction as provided
via MOVs.

DBG_ARM_DISASM=YES llvm-mc -triple=arm-unknown-unknown --disassemble
0xc0 0x00 0xa0 0xe1
Opcode=29 Name=ASR Format=ARM_FORMAT_LDMISCFRM
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	asr	r0, r0, #1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96654 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-19 02:12:06 +00:00
Jim Grosbach
cf43e60544 Radar 7636153. In the presence of large call frames, it's not sufficient
for ARM to just check if a function has a FP to determine if it's safe
to simplify the stack adjustment pseudo ops prior to eliminating frame
indices. Allow targets to override the default behavior and does so for ARM
and Thumb2.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-19 00:16:24 +00:00
Johnny Chen
39a4bb3527 Added LDRD_PRE/POST & STRD_PRE/POST for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96619 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-18 22:31:18 +00:00
Bob Wilson
9f6c4c141f Use NEON vmin/vmax instructions for floating-point selects.
Radar 7461718.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96572 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-18 06:05:53 +00:00
Johnny Chen
adb561d4e0 Added LDRSBT, LDRHT, LDRSHT for disassembly only. And fixed encoding errors
of AI3ldsbpo, AI3ldhpo, and AI3ldshpo in ARMInstrFormats.td in the process.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96565 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-18 03:27:42 +00:00
Johnny Chen
fd6037d613 Added for disassembly only the variants of DMB, DSB, and ISB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96540 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-18 00:19:08 +00:00
Bob Wilson
69bfbd61c6 Remove the NEON N2VSInt instruction class: it's only used in one place and
since it has no pattern, there's not much point in distinguishing an "N2VS"
class for intrinsics anyway.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96525 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-17 22:42:54 +00:00
Johnny Chen
b943627915 Added CLREX (Clear-Exclusive) for disassembly only.
A8.6.30


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-17 22:37:58 +00:00
Bob Wilson
3c0f96e054 More cleanup for NEON:
* Use "S" abbreviation for scalar single FP registers in class and pattern
names, instead of keeping the "D" (for "double") abbreviation and tacking on
an "s" elsewhere in the name.
* Move the scalar single FP register classes and patterns to be more
consistent with other definitions in the file.
* Rename "VNEGf32d" definition to "VNEGfd" for consistency.
* Deleted the N2VDIntsPat pattern; N2VSPat is good enough.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96521 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-17 22:23:11 +00:00
Johnny Chen
fb566795c6 Added RFE for disassembly only.
B6.1.8 RFE Return From Exception loads the PC and the CPSR from the word at the
specified address and the following word respectively.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96519 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-17 21:39:10 +00:00
Chris Lattner
7180f10fc7 add a note, from PR5100
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96490 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-17 18:42:24 +00:00
Johnny Chen
b2503c096f Added BFI for disassembly only.
A8.6.18  BFI - Bitfield insert (Encoding A1)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96462 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-17 06:31:48 +00:00
Bob Wilson
9abe19d0b9 Wrap lines to 80 columns and generally try to clean up whitespace and
indentation.  No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96418 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-17 00:31:29 +00:00
Bob Wilson
0eb0c7401c Handle tGPR register class in a few more places. This fixes some llvm-gcc
build failures due to my fix for pr6111.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96402 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-16 22:01:59 +00:00
Johnny Chen
0296f3e504 Add SMC (Secure Monitor Call) system instruction for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96401 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-16 21:59:54 +00:00
Jim Grosbach
80dc116ce3 80 column cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96393 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-16 21:23:02 +00:00
Jim Grosbach
6417171026 Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96388 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-16 21:07:46 +00:00
Jim Grosbach
39be8fcfdc Update Thumb2 to not use CarryDefIsUnused or CarryDefIsUsed predicates, but
to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96384 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-16 20:42:29 +00:00
Jim Grosbach
cd862b19b8 Remove redundant setting of Defs. CPSR is already marked by the block level set of Defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96383 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-16 20:35:59 +00:00
Jim Grosbach
0a145f3d90 First step in eliminating the CarryDefIsUnused and CarryDefIsUsed predicates.
They won't work with the new ISel mechanism, as Requires predicates are no
longer allowed to reference the node being selected. Moving the predicate to
the patterns instead solves the problem.

This patch handles ARM mode. Thumb2 will follow.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96381 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-16 20:17:57 +00:00
Johnny Chen
64dfb7835d Added for disassembly the following instructions:
o Store Return State (SRSW, SRS)
o Load/Store Coprocessor (LDC/STC and friends)
o MSR (immediate)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96380 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-16 20:04:27 +00:00
Bob Wilson
1665b0a224 Fix pr6111: Avoid using the LR register for the target address of an indirect
branch in ARM v4 code, since it gets clobbered by the return address before
it is used.  Instead of adding a new register class containing all the GPRs
except LR, just use the existing tGPR class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-16 17:24:15 +00:00
Bob Wilson
7dc9747e89 Put repeated empty pattern into the AQI instruction class.
We could almost use a multiclass for the signed/unsigned instructions, but
there are only 6 of them so I guess it's not worth it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96297 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-15 23:43:47 +00:00
Anton Korobeynikov
362dd0bef5 Move TLOF implementations to libCodegen to resolve layering violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96288 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-15 22:37:53 +00:00