Commit Graph

101800 Commits

Author SHA1 Message Date
Tim Northover
69bd9577fc TableGen: avoid dereferencing nullptr variable
ARM64 ended up reaching odder parts of TableGen alias generation than
current backends and caused a segfault.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205089 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 09:03:22 +00:00
Tim Northover
483b0e996c CodeGen: add sensible defaults for the ISD::FROUND operation
Some exotic types didn't know how to handle FROUND, which ARM64 uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205088 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 09:03:18 +00:00
Tim Northover
bc702ae152 MC-exceptions: add support for compact-unwind without .eh_frame
ARM64 has compact-unwind information, but doesn't necessarily want to
emit .eh_frame directives as well. This teaches MC about such a
situation so that it will skip .eh_frame info when compact unwind has
been successfully produced.

For functions incompatible with compact unwind, the normal information
is still written.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205087 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 09:03:13 +00:00
Tim Northover
1db780ba22 CodeGenPrep: wrangle IR to exploit AArch64 tbz/tbnz inst.
Given IR like:
    %bit = and %val, #imm-with-1-bit-set
    %tst = icmp %bit, 0
    br i1 %tst, label %true, label %false

some targets can emit just a single instruction (tbz/tbnz in the
AArch64 case). However, with ISel acting at the basic-block level, all
three instructions need to be together for this to be possible.

This adds another transformation to CodeGenPrep to expose these
opportunities, if targets opt in via the hook.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205086 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 08:22:29 +00:00
Tim Northover
8a272f00a0 MC: add a RefKind field to MCValue
This is principally to allow neater mapping of fixups to relocations
in ARM64 ELF. Without this, there isn't enough information available
to GetRelocType, leading to many more fixup_arm64_... enumerators.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205085 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 08:22:20 +00:00
Tim Northover
1330ee3189 MachO: Add linker-optimisation hint framework to MC.
Another part of the ARM64 backend (so tests will be following soon).
This is currently used by the linker to relax adrp/ldr pairs into nops
where possible, though could well be more broadly applicable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205084 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 07:34:53 +00:00
Tim Northover
0301154c0e MachO: actually set linker-private prefix at MC level.
This was accidentally omitted from r205081.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205083 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 07:33:24 +00:00
Tim Northover
c5d592d5d2 MachO: allow each section to have a linker-private symbol
The upcoming ARM64 backend doesn't have section-relative relocations,
so we give each section its own symbol to provide this functionality.
Of course, it doesn't need to appear in the final executable, so
linker-private is the best kind for this purpose.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205081 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 07:05:06 +00:00
Tim Northover
42529ad33a Make GetCPISymbol a virtual method.
ARM64 for iOS is going to want to emit these symbols in a
linker-private style for efficiency, but other targets probably don't
want that behaviour.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205080 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 07:04:59 +00:00
Tim Northover
7c3e057ff4 Intrinsics: add LLVMHalfElementsVectorType constraint
This is like the LLVMMatchType, except the verifier checks that the
second argument is a vector with the same base type and half the
number of elements.

This will be used by the ARM64 backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205079 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 07:04:54 +00:00
Rafael Espindola
224dbf4aec Completely rewrite ELFObjectWriter::RecordRelocation.
I started trying to fix a small issue, but this code has seen a small fix too
many.

The old code was fairly convoluted. Some of the issues it had:

* It failed to check if a symbol difference was in the some section when
  converting a relocation to pcrel.
* It failed to check if the relocation was already pcrel.
* The pcrel value computation was wrong in some cases (relocation-pc.s)
* It was missing quiet a few cases where it should not convert symbol
  relocations to section relocations, leaving the backends to patch it up.
* It would not propagate the fact that it had changed a relocation to pcrel,
  requiring a quiet nasty work around in ARM.
* It was missing comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205076 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 06:26:49 +00:00
Hal Finkel
44b2b9dc1a [PowerPC] Add subregister classes for f64 VSX values
We had stored both f64 values and v2f64, etc. values in the VSX registers. This
worked, but was suboptimal because we would always spill 16-byte values even
through we almost always had scalar 8-byte values. This resulted in an
increase in stack-size use, extra memory bandwidth, etc. To fix this, I've
added 64-bit subregisters of the Altivec registers, and combined those with the
existing scalar floating-point registers to form a class of VSX scalar
floating-point registers. The ABI code has also been enhanced to use this
register class and some other necessary improvements have been made.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205075 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 05:29:01 +00:00
Saleem Abdulrasool
c06afdcb65 Windows: canonicalise the default windows triple
Canonicalise the default triple that is used on Windows.  This should hopefully
fix the MSVC buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205070 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 01:08:53 +00:00
Akira Hatanaka
b3cb36026a [x86] Fix printing of register operands with q modifier.
Emit 32-bit register names instead of 64-bit register names if the target does
not have 64-bit general purpose registers.

<rdar://problem/14653996>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205067 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 23:28:07 +00:00
David Blaikie
1fc0d63775 Debug Compression: Avoid compression debug_frame for now
Turns out debug_frame does use multiple fragments, so it doesn't
compress correctly with the current approach. Disable compressing it for
now while I figure out what's the best solution for it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205059 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 21:48:31 +00:00
David Majnemer
f3e8b0575d X86: Disable IsLegalToCallImmediateAddr for Win32
WinCOFF cannot form PC relative relocations to support absolute
MCValues.  We should reenable this once WinCOFF supports emission of
IMAGE_REL_I386_REL32 relocations.

This fixes PR19272.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205058 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 21:40:47 +00:00
David Blaikie
8a21cb2433 Add missing include (for r205050)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205053 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 21:00:25 +00:00
David Blaikie
4a9c2585ab llvm-mc: error when -compress-debug-sections is requested and zlib is not linked
This is a bit of a stab in the dark, since I have zlib on my machine.
Just going to bounce it off the bots & see if it sticks.

Do we have some convention for negative REQUIRES: checks? Or do I just
need to add a feature like I've done here?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205050 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 20:45:24 +00:00
Hal Finkel
0e11c017a9 [PowerPC] Fix VSX permutation isel
Not only did I invert the indices when I wrote the code, but I also did the
same thing when I wrote the regression test. Oops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205046 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 20:24:55 +00:00
Rafael Espindola
efd95481bd Convert one last llc -filetype=obj test.
Unfortunately this one fails deep inside the mips backend, so xfail it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205042 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:58:24 +00:00
Hal Finkel
c9de9e60b9 [PowerPC] v2[fi]64 need to be explicitly passed in VSX registers
v2[fi]64 values need to be explicitly passed in VSX registers. This is because
the code in TRI that finds the minimal register class given a register and a
value type will assert if given an Altivec register and a non-Altivec type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205041 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:58:11 +00:00
Rafael Espindola
5811e45fb2 Convert llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205040 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:41:33 +00:00
Rafael Espindola
24845fbabb Convert llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205039 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:38:20 +00:00
Rafael Espindola
830ce8a06e Remove bogus test.
It was using "lc  -filetype=obj" just to pass the result to
"llvm-objdupm -disassemble" and then filecheck assembly.

The CHECK-NOT would never match anyway since it was missing $.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205036 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:26:05 +00:00
Rafael Espindola
e3b7d0228d Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205033 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:19:28 +00:00
Justin Bogner
a655710ce0 Support: Functions for writing endian specific data to streams.
This adds a new header, EndianStream.h, which supplies an adaptor for
writing endian specific data to a raw_ostream.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205032 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:14:43 +00:00
Rafael Espindola
a53735bcf1 Map ELf flags back to more specific section kinds.
With that, convert another llc -filetype=obj test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205031 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 19:14:08 +00:00
Rafael Espindola
be560a3fb7 Parse .gpdword and convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205028 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 18:50:26 +00:00
Rafael Espindola
904658f8d4 convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205027 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 18:34:31 +00:00
Rafael Espindola
6b63578aab Convert "llc -filetype=obj" test into llvm-mc tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205026 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 18:30:07 +00:00
Arnold Schwaighofer
ce36237826 SLPVectorizer: Take credit for free extractelement instructions
Extract element instructions that will be removed when vectorzing lower the
cost.

Patch by Arch D. Robison!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205020 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 17:21:32 +00:00
Arnold Schwaighofer
aa0a2a35f8 SLPVectorizer: Fix typos
Patch by Arch D. Robison!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205019 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 17:21:27 +00:00
Arnold Schwaighofer
b48eb2cdaa SLPVectorizer: Ignore users that are insertelements we can reschedule them
Patch by Arch D. Robison!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205018 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 17:21:22 +00:00
Mark Seaborn
e2591680b4 Exception handling docs: Clarify how the llvm.eh.* intrinsics are used
The non-SJLJ and SJLJ intrinsics are generated by the frontend and
backend respectively.

Differential Revision: http://llvm-reviews.chandlerc.com/D3010

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205017 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 17:08:57 +00:00
David Blaikie
b91f51161f Only test compression when linked with zlib.
I'll implement error handling and a negative test in both llvm-mc and
Clang soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205016 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 17:04:53 +00:00
Rafael Espindola
ffc7e0f678 Add const to a method I missed in the previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205014 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 16:14:12 +00:00
Rafael Espindola
3a2bbc9bf4 Add const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205013 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 16:06:09 +00:00
Erik Verbruggen
76eb786cf7 Revert "InstCombine: merge constants in both operands of icmp."
This reverts commit r204912, and follow-up commit r204948.

This introduced a performance regression, and the fix is not completely
clear yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205010 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 14:50:57 +00:00
Erik Verbruggen
cc58a593a2 Revert "GVN: merge overflow intrinsics with non-overflow instructions."
This reverts commit r203553, and follow-up commits r203558 and r203574.

I will follow this up on the mailinglist to do it in a way that won't
cause subtle PRE bugs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205009 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 14:42:34 +00:00
Christian Pirker
1f072c36d0 Add ARM big endian Target (armeb, thumbeb)
Reviewed at http://llvm-reviews.chandlerc.com/D3095



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205007 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 14:35:30 +00:00
Tim Northover
bd2cca79b7 R600: avoid calling std::next on an iterator that might be end()
This was causing my llc to go into an infinite loop on
CodeGen/R600/address-space.ll (just triggered recently by some allocator
changes).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205005 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 13:52:56 +00:00
Tim Northover
b7de4288bc Intrinsics: expand semantics of LLVMExtendedVectorType (& trunc)
These are used in the ARM backends to aid type-checking on patterns involving
intrinsics. By making sure one argument is an extended/truncated version of
another.

However, there's no reason to limit them to just vectors types. For example
AArch64 has the instruction "uqshrn sD, dN, #imm" which would naturally use an
intrinsic taking an i64 and returning an i32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205003 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 12:31:39 +00:00
Chandler Carruth
efb8deb640 [Allocator Cleanup] Sink the private data members and methods to the
bottom of the interface to make it easier to scan and find the public
API.

No functionality changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204996 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 09:18:42 +00:00
Chandler Carruth
0e4c26eedc [Allocator Cleanup] Move generic pointer alignment helper out of an
out-of-line private static method and into the collection of inline
alignment helpers in MathExtras.h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204995 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 09:08:14 +00:00
Chandler Carruth
415a008ad2 [Allocator Cleanup] Make the growth of the "slab" size of the
BumpPtrAllocator significantly less strange by making it a simple
function of the number of slabs allocated rather than by making it
a recurrance. I *think* the previous behavior was essentially that the
size of the slabs would be doubled after the first 128 were allocated,
and then doubled again each time 64 more were allocated, but only if
every allocation packed perfectly into the slab size. If not, the wasted
space wouldn't be counted toward increasing the size, but allocations
over the size threshold *would*. And since the allocations over the size
threshold might be much larger than the slab size, this could have
somewhat surprising consequences where we rapidly grow the slab size.

This currently requires adding state to the allocator to track the
number of slabs currently allocated, but that isn't too bad. I'm
planning further changes to the allocator that will make this state fall
out even more naturally.

It still doesn't fully decouple the growth rate from the allocations
which are over the size threshold. That fix is coming later.

This specific fix will allow making the entire thing into a more
stateless device and lifting the parameters into template parameters
rather than runtime parameters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204993 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 08:53:25 +00:00
Chandler Carruth
ec90ab499d [cleanup] Hoist the initialization and constants for slab sizes to the
top of the default jit memory manager. This will allow them to be used
as template parameters rather than runtime parameters in a subsequent
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204992 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 08:53:08 +00:00
David Blaikie
2559cde2e8 PBQP: Minor cleanups to r204857
* Use assignment instead of swap (since the original value is being
  destroyed anyway)

* Rename "updateAdjEdgeId" to "setAdjEdgeId"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204983 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 23:42:21 +00:00
Adrian Prantl
cf6f4c8c34 C++11: convert verbose loops to range-based loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204981 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 23:30:04 +00:00
Hal Finkel
e2ee98ab16 [PowerPC] Use a small cleanup pass to remove VSX self copies
As explained in r204976, because of how the allocation of VSX registers
interacts with the call-lowering code, we sometimes end up generating self VSX
copies. Specifically, things like this:
  %VSL2<def> = COPY %F2, %VSL2<imp-use,kill>
(where %F2 is really a sub-register of %VSL2, and so this copy is a nop)

This adds a small cleanup pass to remove these prior to post-RA scheduling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204980 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 23:12:31 +00:00
Manman Ren
d9524d66cd Provide a target override for the cost of using a callee-saved register
for the first time.

Thanks Andy for the discussion.
rdar://16162005


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204979 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 23:10:04 +00:00