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26 Commits

Author SHA1 Message Date
Eric Christopher
88d724909e In preparation for moving ARM's TargetRegisterInfo to the TargetMachine 
merge Thumb1RegisterInfo and Thumb2RegisterInfo. This will enable
us to match the TargetMachine for our TargetRegisterInfo classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232117 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-12 22:48:50 +00:00
James Molloy
40ae57cc0a Fix the Load/Store optimization pass to work with Thumb1. 
Patch by Moritz Roth!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208992 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-16 14:14:30 +00:00
Gordon Keiser
93b10789c6 Testing commit access to llvm. Remove two lines of whitespace from the Thumb README. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178256 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-28 18:26:15 +00:00
Nick Lewycky
e45f2dfde6 Add another note taken from the gcc bugzilla. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123315 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-12 09:06:19 +00:00
Jim Grosbach
e5165490b7 Use Unified Assembly Syntax for the ARM backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-09 00:11:35 +00:00
Jim Grosbach
6009751244 Enable allocation of R3 in Thumb1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84563 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 22:57:03 +00:00
Evan Cheng
3c91f36a45 Another TODO. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77026 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 00:39:37 +00:00
Evan Cheng
f6fe957950 Fix PR4567. Thumb1 target was using the wrong instruction to handle sp = sub fp, #c. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76401 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 06:59:32 +00:00
Evan Cheng
2f297df02e Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75360 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 07:08:13 +00:00
Evan Cheng
446c428bf3 Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. 
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 06:43:01 +00:00
Evan Cheng
b6264decdb More info about Thumb1 predication support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75220 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 02:10:17 +00:00
Evan Cheng
896fe89f55 Another todo entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75192 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 23:17:28 +00:00
Evan Cheng
6dded67b0d Add a Thumb readme entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75173 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 20:50:52 +00:00
Jim Grosbach
1a6c683315 Whitespace cleanup. Test commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54695 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-12 18:34:45 +00:00
Evan Cheng
4102eb57bb Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43234 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-22 22:11:27 +00:00
Chris Lattner
c621ae7bba update this entry, now that Anton implemented shift/and lowering for 
switches.  There is one really easy isel thing here with tst we are not
getting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37400 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-02 18:45:14 +00:00
Evan Cheng
87c6c9abb3 New entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35480 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-29 21:40:13 +00:00
Evan Cheng
5603dcf21e New entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35206 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 08:10:17 +00:00
Evan Cheng
2ef02a220e New entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34000 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-07 09:22:15 +00:00
Evan Cheng
1f253d6e97 Update 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33998 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-07 08:37:57 +00:00
Evan Cheng
8e59ea998f Spill / restore should avoid modifying the condition register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33971 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-07 00:06:56 +00:00
Evan Cheng
736cefff85 Add a note. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33743 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-01 02:46:20 +00:00
Evan Cheng
5b49ab9996 Possible JT improvements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33733 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-01 01:07:48 +00:00
Evan Cheng
11a065e599 Add entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33723 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-31 22:11:38 +00:00
Evan Cheng
198529aaf1 New entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33569 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-27 02:33:22 +00:00
Evan Cheng
a8e2989ece ARM backend contribution from Apple. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-19 07:51:42 +00:00