6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-25 19:29:53 +00:00
Code Issues Projects Releases Wiki Activity
104,621 Commits 39 Branches 0 Tags
Commit Graph

941 Commits

Author SHA1 Message Date
Tom Stellard
6b0a08b15b R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210869 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-13 01:32:00 +00:00
Tom Stellard
ee0f3892f9 R600: Drop use of cached TargetMachine in R600InstrInfo.cpp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210868 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-13 01:31:56 +00:00
Tom Stellard
aa48b83e80 R600: Drop use of cached TargetMachine in AMDGPUInstrInfo.cpp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210865 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-13 01:02:57 +00:00
Matt Arsenault
00c3986254 R600: Mostly remove remaining AMDIL intrinsics. 
Delete all unused ones, and add new AMDGPU named intrinsics for
the ones that are. Handle the old AMDIL names for comptability (although
remove their GCCBuiltin names) and add tests since there weren't any
for these before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210827 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-12 21:15:44 +00:00
Matt Arsenault
0b87955888 R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec* 
There is not such thing as a 0-data ds instruction, and the data
operand needs to be a vgpr set to something meaningful.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210756 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-12 08:21:54 +00:00
Tom Stellard
beef5c58d7 R600: Set correct InstrItinClass for instructions using *Helper classes 
We weren't doing this before, so all instruction using the *Helper
classes were considered for any ALU slot.

This fixes a hang in the builtin-char-clz-1.0.generated.cl piglit test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210703 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 20:51:42 +00:00
Tom Stellard
7ae77a1b1e R600: BCNT_INT is a vector only instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210702 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 20:51:39 +00:00
Matt Arsenault
7fa80b45eb R600/SI: Fix bitcast between v2i32 and f64 
This is the same problem fixed in r210664 for more types.

The test passes without this fix. For some reason
I'm only hitting this when creating selects lowered
to v2i32 selects.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210692 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 19:31:13 +00:00
Matt Arsenault
4600175c7f R600/SI: Update place using old subtarget predicate 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210683 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 18:11:34 +00:00
Matt Arsenault
c9dbd0da7a R600/SI: Add common 64-bit LDS atomics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210680 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 18:08:54 +00:00
Matt Arsenault
481a071a8b R600/SI: Add instruction definitions for 64-bit LDS atomics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210679 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 18:08:50 +00:00
Matt Arsenault
6b19a3a474 R600/SI: Add 32-bit LDS atomic cmpxchg 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210678 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 18:08:48 +00:00
Matt Arsenault
a396a70c1d R600/SI: Use LDS atomic inc / dec 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210677 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 18:08:45 +00:00
Matt Arsenault
2da1a85cbb R600/SI: Add other LDS atomic operations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210676 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 18:08:42 +00:00
Matt Arsenault
507d8cad7b R600/SI: Add instruction definitions for more LDS ops 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210675 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 18:08:39 +00:00
Matt Arsenault
4a19dd468d R600/SI: Fix backwards names for local atomic instructions. 
The manual lists them as *_RTN_U32, not *_U32_RTN, which is more
consistent with how every other sized instruction is named.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210674 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 18:08:37 +00:00
Matt Arsenault
b97095b94f R600/SI: Refactor local atomics. 
Use patterns that will also match the immediate offset to
match the normal read / writes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210673 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 18:08:34 +00:00
Matt Arsenault
8a9df8f92c R600/SI: Use v_cvt_f32_ubyte* instructions 
This eliminates extra extract instructions when loading an i8 vector to
a float vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210666 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 17:50:44 +00:00
Matt Arsenault
a2dca4cc04 R600/SI: Fix selection failure on scalar_to_vector 
There seem to be only 2 places that produce these,
and it's kind of tricky to hit them.

Also fixes failure to bitcast between i64 and v2f32,
although this for some reason wasn't actually broken in the
simple bitcast testcase, but did in the scalar_to_vector one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210664 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 17:40:32 +00:00
Rafael Espindola
e12b0bbc02 Try to fix the msvc build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210636 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 04:41:37 +00:00
Matt Arsenault
3692045d8e Use cast instead of assert + dyn_cast 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210628 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 03:30:06 +00:00
Matt Arsenault
e0162b9648 R600: Add helper functions. 
Extract these from some of my other patches, since this
is the only thing really making them dependent on each other.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210627 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 03:29:54 +00:00
Tom Stellard
cd0b8d6cbf R600/SI: Emit an error when attempting to spill VGPRs v4 
I can't get VGPR spilling to work reliable, so for now just emit
an error when the register allocator tries to spill VGPRs.

v2:
  - Fix build
v3:
  - Added crash fix when spilling SPGRs
v4:
  - Use V_MOV_B32 as a dummy instruction instead of S_NOP

Patch by: Darren Powell

https://bugs.freedesktop.org/show_bug.cgi?id=75276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210588 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 21:20:41 +00:00
Tom Stellard
48d11b0228 R600/SI: Fix a crash when spilling SGPRs 
We need to make sure only one new instruction is added when spilling
otherwise the register allocator may crash.

This fixes a crash in the game Antichamber.

https://bugs.freedesktop.org/show_bug.cgi?id=75276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210587 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 21:20:38 +00:00
Matt Arsenault
1f4772305a R600: Use BCNT_INT for evergreen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210569 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 19:18:28 +00:00
Matt Arsenault
69891c0115 R600/SI: Implement i64 ctpop 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210568 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 19:18:24 +00:00
Matt Arsenault
ee9772d9dd R600/SI: Use bcnt instruction for ctpop 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210567 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 19:18:21 +00:00
Matt Arsenault
bfd00e21b7 R600: Handle fcopysign 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210564 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 19:00:20 +00:00
Matt Arsenault
0ba78a9121 R600/SI: Handle sign_extend and zero_extend to i64 with patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210563 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 18:54:59 +00:00
Tom Stellard
f586a260ca SelectionDAG: Expand SELECT_CC to SELECT + SETCC 
This consolidates code from the Hexagon, R600, and XCore targets.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210539 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 16:01:22 +00:00
Matt Arsenault
405ed284b7 R600/SI: Rename VOP3 helper class to be more general 
It has other uses besides shift instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210478 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-09 17:00:46 +00:00
Matt Arsenault
1968da36ed R600/SI: Keep 64-bit not on SALU 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210476 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-09 16:36:31 +00:00
Matt Arsenault
cf7a113d2f R600: Fix selection failure for vector bswap 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210475 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-09 16:20:25 +00:00
Matt Arsenault
798a829eca R600/SI: Match rsq instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210226 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-05 00:15:55 +00:00
Matt Arsenault
6db82d3819 Use nullptr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210222 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-05 00:01:12 +00:00
Matt Arsenault
1b68686365 Fix typos 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210135 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-03 23:06:13 +00:00
Matt Arsenault
3871a03035 R600: Set all float vector expands in the same place 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209988 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-01 07:38:21 +00:00
Matt Arsenault
606b80c8c4 R600/SI: Remove redundant patterns 
These patterns are already handled in the instruction definition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209979 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-31 19:25:17 +00:00
Matt Arsenault
da5824d073 R600/SI: Fix [s|u]int_to_fp for i1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209971 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-31 06:47:42 +00:00
Matt Arsenault
bf933548ba R600/SI: Fix pattern variable names. 
These are confusing enough since the order swaps,
so give them more useful names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209787 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-29 01:18:01 +00:00
Matt Arsenault
fed4bab148 R600: Add definition for flat address space ID. 
Use 4 since that's probably what it will be for spir.
Move ADDRESS_NONE to the end to keep the constant_buffer_* values
unchanged, since apparently a bunch of r600 tests use those directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209463 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:27:07 +00:00
Matt Arsenault
3c698f35e0 R600: Try to convert BFE back to standard bit ops when possible. 
This allows existing DAG combines to work on them, and then
we can re-match to BFE if necessary during instruction selection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209462 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:09:12 +00:00
Matt Arsenault
e3ed404672 R600: Add dag combine for BFE 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209461 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:09:07 +00:00
Matt Arsenault
7e12b82625 R600: Implement ComputeNumSignBitsForTargetNode for BFE 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209460 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:09:03 +00:00
Matt Arsenault
9859540b06 R600: Implement computeMaskedBitsForTargetNode for BFE 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209459 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:09:00 +00:00
Matt Arsenault
cb0402e9a4 R600: Expand mul24 for GPUs without it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209458 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:00:24 +00:00
Matt Arsenault
21851f9adb R600: Expand mad24 for GPUs without it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209457 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:00:20 +00:00
Matt Arsenault
f49da4338a R600: Add intrinsics for mad24 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209456 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:00:15 +00:00
Matt Arsenault
351c658fc2 R600/SI: Move instruction pattern to instruction definition 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209454 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 17:45:20 +00:00
Matt Arsenault
bce7d05ba9 R600/SI: Match fp_to_uint / uint_to_fp for f64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209388 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 03:20:30 +00:00