Commit Graph

81 Commits

Author SHA1 Message Date
Chandler Carruth
4ffd89fa4d Sort the #include lines for utils/...
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04 10:37:14 +00:00
Joerg Sonnenberger
61131ab15f Remove exception handling usage from tblgen.
Most places can use PrintFatalError as the unwinding mechanism was not
used for anything other than printing the error. The single exception
was CodeGenDAGPatterns.cpp, where intermediate errors during type
resolution were ignored to simplify incremental platform development.
This use is replaced by an error flag in TreePattern and bailout earlier
in various places if it is set. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25 20:33:17 +00:00
Jakob Stoklund Olesen
f104bf65b9 Add CodeGenTarget::guessInstructionProperties.
Currently, TableGen just guesses instruction properties when it can't
infer them form patterns.

This adds a guessInstructionProperties flag to the instruction set
definition that will be used to disable guessing. The flag is intended
as a migration aid. It will be removed again when no more targets need
their properties guessed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23 19:34:41 +00:00
Andrew Trick
2661b411cc I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07 04:00:00 +00:00
Jim Grosbach
194f3fa9ea Revert "Emit the SubRegTable with the smallest possible integer type."
This reverts commit 151760.

We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo,
but to do that, the type of the lookup table needs to be the same for
all targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 17:30:35 +00:00
Benjamin Kramer
b9ace0215d Emit the SubRegTable with the smallest possible integer type.
Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151760 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 21:57:08 +00:00
Devang Patel
0dbcadaa2f Split AsmParser into two components - AsmParser and AsmParserVariant
AsmParser holds info specific to target parser.
AsmParserVariant holds info specific to asm variants supported by the target.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147787 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09 19:13:28 +00:00
Peter Collingbourne
7c78888887 Move TableGen's parser and entry point into a library
This is the first step towards splitting LLVM and Clang's tblgen executables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 16:41:13 +00:00
Jakob Stoklund Olesen
29f018cee6 Switch to ArrayRef<CodeGenRegisterClass*>.
This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140816 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 22:28:37 +00:00
Owen Anderson
bea6f615ee Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0.
Patch by Jim Grosbach.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 21:06:21 +00:00
Jakob Stoklund Olesen
abdbc84b4e Store CodeGenRegisters as pointers so they won't be reallocated.
Reuse the CodeGenRegBank DenseMap in a few places that would build their
own or use linear search.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133333 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18 04:26:06 +00:00
Jakob Stoklund Olesen
7b9cafde5e Move the list of register classes into CodeGenRegBank as well.
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133029 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 00:20:40 +00:00
Jakob Stoklund Olesen
b5923db192 Move the list of registers into CodeGenRegBank.
Also move the sub-register index computations from RegisterInfoEmitter
into CodeGenRegBank.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132865 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-11 00:28:06 +00:00
Jakob Stoklund Olesen
dc29c44713 Move some sub-register index calculations to CodeGenRegisters.cpp
Create a new CodeGenRegBank class that will eventually hold all the code
that computes the register structure from Records.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132849 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-10 18:40:00 +00:00
Jakob Stoklund Olesen
123cab9480 Teach TableGen to automatically generate missing SubRegIndex instances.
The RegisterInfo.td file should only specify the indexes that sources need to
refer to. The rest is inferred.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131058 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-07 21:22:39 +00:00
Jim Grosbach
510207cb1e Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127447 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 01:27:24 +00:00
Chris Lattner
036609bd7d Flag -> Glue, the ongoing saga
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23 18:28:41 +00:00
Chris Lattner
67db883487 eliminate the Records global variable, patch by Garrison Venn!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121659 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 00:23:57 +00:00
Chris Lattner
ec6f096c36 a bunch of random cleanup, move a helper to CGT where it belongs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118031 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 18:10:06 +00:00
Chris Lattner
52a261b3c1 fix a long standing wart: all the ComplexPattern's were being
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 20:31:19 +00:00
Jakob Stoklund Olesen
48d0c163fb Ignore NumberHack and give each SubRegIndex instance a unique enum value instead.
This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.

Then I'll remove NumberHack entirely.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104615 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:21:04 +00:00
Jakob Stoklund Olesen
09bc029865 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 21:46:58 +00:00
Chris Lattner
e8cabf3c2e add a new SDNPVariadic SDNP node flag, and use it in
dag isel gen instead of instruction properties.  This
allows the oh-so-useful behavior of matching a variadic
non-root node.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 05:07:09 +00:00
Chris Lattner
e14d2e210d Finally change the instruction looking map to be a densemap from
record* -> instrinfo instead of std::string -> instrinfo.

This speeds up tblgen on cellcpu from 7.28 -> 5.98s with a debug
build (20%).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98916 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 01:07:44 +00:00
Chris Lattner
6a91b18e57 make inst_begin/inst_end iterate over InstructionsByEnumValue.
Use CodeGenTarget::getInstNamespace in one place and fix it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 01:00:55 +00:00
Chris Lattner
01dcecc214 revert 98912
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98914 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:50:47 +00:00
Chris Lattner
a28bc686fa make inst_begin/inst_end iterate over InstructionsByEnumValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98912 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:40:22 +00:00
Chris Lattner
f65027842e change Target.getInstructionsByEnumValue to return a reference
to a vector that CGT stores instead of synthesizing it on every 
call.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98910 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:34:35 +00:00
Chris Lattner
b61e09de6d don't go through getInstructions().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98906 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:18:23 +00:00
Chris Lattner
f30187a363 look up instructions by record, not by name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:07:20 +00:00
Chris Lattner
2cacec55f9 Completely rewrite tblgen's type inference mechanism,
changing the primary datastructure from being a 
"std::vector<unsigned char>" to being a new TypeSet class
that actually has (gasp) invariants!

This changes more things than I remember, but one major
innovation here is that it enforces that named input 
values agree in type with their output values.

This also eliminates code that transparently assumes (in 
some cases) that SDNodeXForm input/output types are the
same, because this is wrong in many case.

This also eliminates a bug which caused a lot of ambiguous
patterns to go undetected, where a register class would
sometimes pick the first possible type, causing an
ambiguous pattern to get arbitrary results.

With all the recent target changes, this causes no 
functionality change!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98534 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-15 06:00:16 +00:00
Dan Gohman
537ab90d8d Remove the CPAttrParentAsRoot code, which is unused, and inconvenient
for a refactoring I'm working on.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92503 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-04 20:31:55 +00:00
Chris Lattner
c128b3e74e clang++ points out that this is pointless.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86239 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-06 06:33:01 +00:00
Owen Anderson
825b72b057 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 20:47:22 +00:00
Owen Anderson
e50ed30282 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 22:56:29 +00:00
Daniel Dunbar
0e2771f4c4 Match X86 register names to number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77404 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29 00:02:19 +00:00
Daniel Dunbar
1a55180238 Replace std::iostreams with raw_ostream in TableGen.
- Sorry, I can't help myself.

 - No intended functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74742 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03 00:10:29 +00:00
Dale Johannesen
874ae251c3 Revert 72707 and 72709, for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02 03:12:52 +00:00
Dale Johannesen
4150d83abe Make the implicit inputs and outputs of target-independent
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag.  Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.

Most targets will still produce a Flag-setting target-dependent
version when selection is done.  X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc.  This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted.  All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly.  The
same can be done on other targets.

The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72707 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-01 23:27:20 +00:00
Dan Gohman
8a17870da4 Generalize getRegisterClassForRegister to handle registers
in multiple classes in the case that the classes are all
in subset/superset relations. This function is used by the
fast-isel emitter, which always wants the super-most set.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68957 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 15:24:11 +00:00
Dan Gohman
1e0ee4bc38 Factor the code for determining the target-specific instruction
namespace out of the isel emitters and into common code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55079 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-20 21:45:57 +00:00
Mon P Wang
2887310630 Added MemOperands to Atomic operations since Atomics touches memory.
Added abstract class MemSDNode for any Node that have an associated MemOperand
Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and
atomic.lss => atomic.load.sub


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52706 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-25 08:15:39 +00:00
Duncan Sands
83ec4b6711 Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-06 12:08:01 +00:00
Dan Gohman
ee4fa1977d Move instruction flag inference out of InstrInfoEmitter and into
CodeGenDAGPatterns, where it can be used in other tablegen backends.
This allows the inference to be done for DAGISelEmitter so that it
gets accurate mayLoad/mayStore/isSimpleLoad flags. 

This brings MemOperand functionality back to where it was before
48329. However, it doesn't solve the problem of anonymous patterns
which expand to code that does loads or stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49123 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-03 00:02:49 +00:00
Christopher Lamb
8535624739 Allow ComplexExpressions in InstrInfo.td files to be slightly more... complex! ComplexExpressions can now have attributes which affect how TableGen interprets
the pattern when generating matchin code. 

The first (and currently, only) attribute causes the immediate parent node of the ComplexPattern operand to be passed into the matching code rather than the node at the root of the entire DAG containing the pattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46606 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-31 07:27:46 +00:00
Chris Lattner
bc0b9f70ae start inferring 'no side effects'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45822 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10 05:39:30 +00:00
Chris Lattner
710e995889 realize that instructions who match intrinsics that read memory read memory.
Also, instructions with any nodes that are SDNPMayLoad also read memory.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45817 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10 04:38:57 +00:00
Chris Lattner
c8478d8b12 Change the 'isStore' inferrer to look for 'SDNPMayStore'
instead of "ISD::STORE".  This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores).  This allows us to remove
more explicit isStore flags from the .td files.

Finally, add a warning for when a .td file contains an explicit 
isStore and tblgen is able to infer it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45654 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-06 06:44:58 +00:00
Chris Lattner
6cefb77a70 change getQualifiedName to be a global function.
Split the pattern parsing code out from the dag isel emitter into it's own file.

No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45632 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-05 22:25:12 +00:00
Chris Lattner
3060910e29 remove attributions from utils.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45419 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:37:13 +00:00