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2872 Commits

Author SHA1 Message Date
Craig Topper
8030e1a0df Add ifdef around getSubtargetFeatureName in tablegen output file so that only targets that want the function get it. This prevents other targets from getting an unused function warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155538 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-25 06:56:34 +00:00
Jim Grosbach
14ce6fac24 ARM: improved assembler diagnostics for missing CPU features. 
When an instruction match is found, but the subtarget features it
requires are not available (missing floating point unit, or thumb vs arm
mode, for example), issue a diagnostic that identifies what the feature
mismatch is.

rdar://11257547

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155499 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-24 22:40:08 +00:00
Craig Topper
f0ae38ef2e Remove 'XXXRegisterClass' from tablegen output. Targets should use '&XXXRegClass' instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155270 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-21 01:49:25 +00:00
Andrew Trick
7c0903a924 TableGen'd RegPressure: Added getPressureSetName. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155234 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-20 20:44:58 +00:00
Jim Grosbach
c1922c72ad TableGen support for auto-generating assembly two-operand aliases. 
Assembly matchers for instructions with a two-operand form. ARM is full
of these, for example:
  add {Rd}, Rn, Rm  // Rd is optional and is the same as Rn if omitted.

The property TwoOperandAliasConstraint on the instruction definition controls
when, and if, an alias will be formed. No explicit InstAlias definitions
are required.

rdar://11255754

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155172 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-19 23:59:23 +00:00
Jim Grosbach
b423d18a00 Use a SmallVector instead of std::vector for ResOperands. 
There's almost always a small number of instruction operands, so
use a SmallVector and save on heap allocations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155143 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-19 17:52:34 +00:00
Jim Grosbach
8caecdea56 Update some internal naming conventions to modern style. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155142 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-19 17:52:32 +00:00
Craig Topper
9b58f29ad0 Make fast isel use &XXXRegClass instead of XXXRegisterClass. Not a functional change since XXXRegisterClass is just a constant alias of &XXXRegClass, but should probably go away. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155104 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-19 06:52:06 +00:00
Jim Grosbach
d4824fc8aa Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155075 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 23:46:25 +00:00
Jim Grosbach
b4b26f87fe Revert "Replace some uses of std:map<std::string,...> with StringMap." 
StringMap iterators are not deterministic, and that's more important
here than speed or memory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155039 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 20:24:49 +00:00
Benjamin Kramer
3cbcffc4e5 tblgen: remove duplicated newlines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155038 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 19:22:47 +00:00
Jim Grosbach
325478d78d Replace some uses of std:map<std::string,...> with StringMap. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155037 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 19:13:59 +00:00
Jim Grosbach
a5b0685142 Use SmallVector for the requirements on an InstAlias. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155034 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 19:02:43 +00:00
Jim Grosbach
016c679c50 Tidy up. Formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155032 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 18:56:33 +00:00
Jim Grosbach
bfb4327baa Move a few more warnings to use PrintWarning(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155027 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 18:39:31 +00:00
Jim Grosbach
37c53ff6a7 Tidy up. No need for a Twine here, as it's just constants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155026 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 18:39:27 +00:00
Jim Grosbach
723fc11f91 Formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155025 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 18:39:23 +00:00
Jim Grosbach
5bd9e0dd02 Tidy up. Add a '.' at the end of the sentence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155024 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 18:39:19 +00:00
Jim Grosbach
7be43977b4 Clean up warning text. Remove extraneous prefix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155015 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 18:09:50 +00:00
Jim Grosbach
9b29ea4eb3 TableGen use PrintWarning rather than fprintf(stderr,...) for warnings. 
That way we get source line number information from the diagnostics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155014 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 17:46:41 +00:00
Silviu Baranga
e546c4c9c3 Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155000 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-18 13:02:55 +00:00
Jim Grosbach
67cd20d039 Sanity check error handling for TokenAlias. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154951 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-17 21:23:52 +00:00
Jim Grosbach
65da6fc8af Tidy up. 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154881 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-17 00:01:04 +00:00
Craig Topper
b57b170317 Fix target specific intrinsic handling to adjust intrinsic number before doing attribute table lookup. Also fix attribute table lookup to handle 'invalid' intrinsic correctly. Fixes PR12542 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154658 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-13 06:14:57 +00:00
Jim Grosbach
2ce182c90c Remove incorrect comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154533 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 21:09:54 +00:00
Jim Grosbach
11fc6467e6 Tidy up. Remove hard tab characters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154532 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 21:02:33 +00:00
Jim Grosbach
bf1aab1507 Tidy up. Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154531 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 21:02:30 +00:00
Andrew Trick
ec14cd7ddc TableGen's regpressure: emit per-registerclass weight limits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154518 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 18:16:28 +00:00
Andrew Trick
5c1761d486 TableGen'd regpressure: register unit set pruning. 
The pruning is more complete if it is not done incrementally. The code
is also a tad less convluted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154510 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 17:35:26 +00:00
Andrew Trick
680363b5fd Tablegen'd regpressure: emit the weighted pressure limit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154477 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 04:31:33 +00:00
Andrew Trick
aa744e2c44 Table-generated register pressure fixes. 
Handle mixing allocatable and unallocatable register gracefully.
Simplify the pruning of register unit sets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154474 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 03:19:15 +00:00
Andrew Trick
4b745588c9 TableGen/reginfo potential bug: typo from previous checkin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154452 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-10 23:53:32 +00:00
Andrew Trick
0fb0678106 Fix for register pressure tables. 
Recent refactoring introduced a bug. Fix: added buildRegUnitSets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154382 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-10 03:36:49 +00:00
Andrew Trick
c72e08b4a9 Use std::includes instead of my own implementation. 
Jakob's review.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154377 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-10 03:12:29 +00:00
Andrew Trick
176194d4ee Added register unit sets to the target description. 
This is a new algorithm that finds sets of register units that can be
used to model registers pressure. This handles arbitrary, overlapping
register classes. Each register class is associated with a (small)
list of pressure sets. These are the dimensions of pressure affected
by the register class's liveness.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154374 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-10 02:25:24 +00:00
Andrew Trick
d35ac3c8bc Added register unit weights to the target description. 
This is a new algorithm that associates registers with weighted
register units to accuretely model their effect on register
pressure. This handles registers with multiple overlapping
subregisters. It is possible, but almost inconceivable that the
algorithm fails to find an exact solution for a target description. If
an exact solution cannot be found, an inexact, but reasonable solution
will be chosen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154373 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-10 02:25:21 +00:00
Andrew Trick
aec111a06b Fix header comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154372 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-10 02:25:18 +00:00
Craig Topper
58609b7413 Convert assert(false) followed by a return to llvm_unreachable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153997 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-04 04:55:46 +00:00
Craig Topper
9b1b25f063 Tidy up spacing in some tablegen outputs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153937 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 06:52:47 +00:00
Craig Topper
769bbfd951 Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 05:20:24 +00:00
Andrew Trick
5aeda3f076 Cleanup set_union usage. The same thing but a bit cleaner now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153922 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 01:35:52 +00:00
Andrew Trick
f1275959b2 Use std::set_union instead of nasty custom code. 
I just noticed Jakob's examples of the proper application of
std::set... routines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153918 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 00:47:23 +00:00
Silviu Baranga
545b962f15 Second part for the 153874 one 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153875 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 15:46:46 +00:00
Benjamin Kramer
94338594ef Emit the asm writer's mnemonic table with SequenceToOffsetTable. 
This way we can get AVX v-prefixed instructions tail merged with the normal insns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153869 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 09:13:46 +00:00
Craig Topper
fab3f7ee6f Reorder fields in MatchEntry and OperandMatchEntry to reduce padding. A bit tricky due to the target specific sizes for some of the fields so the ordering is only optimal for the targets in the tree. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153865 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 07:48:39 +00:00
Craig Topper
7c0b3c1fb6 Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153863 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 07:01:04 +00:00
Craig Topper
a4bd58b0f0 Use SequenceToOffsetTable to generate instruction name table for AsmWriter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153857 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 00:47:39 +00:00
Craig Topper
413b2e7539 Use SequenceToOffsetTable to create instruction name table. Saves space particularly on X86 where AVX instructions just add a 'v' to the front of other instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153841 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-01 18:14:14 +00:00
Benjamin Kramer
243018ffcf Emit the LLVM<->DWARF register mapping as a sorted table and use binary search to do the lookup. 
This also avoids emitting the information twice, which led to code bloat. On i386-linux-Release+Asserts
with all targets built this change shaves a whopping 1.3 MB off clang. The number is probably exaggerated
by recent inliner changes but the methods were already enormous with the old inline cost computation.

The DWARF reg -> LLVM reg mapping doesn't seem to have holes in it, so it could be a simple lookup table.
I didn't implement that optimization yet to avoid potentially changing functionality.

There is still some duplication both in tablegen and the generated code that should be cleaned up eventually.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153837 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-01 14:23:58 +00:00
Andrew Trick
9f2a9d741f comment typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153796 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-31 02:39:17 +00:00