30 Commits

Author SHA1 Message Date
Andrea Di Biagio
53daaff125 [X86] Improved lowering of v4x32 build_vector dag nodes.
This patch improves the lowering of v4f32 and v4i32 build_vector dag nodes
that are known to have at least two non-zero elements.

With this patch, a build_vector that performs a blend with zero is 
converted into a shuffle. This is done to let the shuffle legalizer expand
the dag node in a optimal way. For example, if we know that a build_vector
performs a blend with zero, we can try to lower it as a movq/blend instead of
always selecting an insertps.

This patch also improves the logic that lowers a build_vector into a insertps
with zero masking. See for example the extra test cases added to test sse41.ll.

Differential Revision: http://reviews.llvm.org/D6311


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222375 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 19:34:29 +00:00
Chandler Carruth
03a77831cc [x86] Enable the new vector shuffle lowering by default.
Update the entire regression test suite for the new shuffles. Remove
most of the old testing which was devoted to the old shuffle lowering
path and is no longer relevant really. Also remove a few other random
tests that only really exercised shuffles and only incidently or without
any interesting aspects to them.

Benchmarking that I have done shows a few small regressions with this on
LNT, zero measurable regressions on real, large applications, and for
several benchmarks where the loop vectorizer fires in the hot path it
shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy
Bridge machines. Running on AMD machines shows even more dramatic
improvements.

When using newer ISA vector extensions the gains are much more modest,
but the code is still better on the whole. There are a few regressions
being tracked (PR21137, PR21138, PR21139) but by and large this is
expected to be a win for x86 generated code performance.

It is also more correct than the code it replaces. I have fuzz tested
this extensively with ISA extensions up through AVX2 and found no
crashes or miscompiles (yet...). The old lowering had a few miscompiles
and crashers after a somewhat smaller amount of fuzz testing.

There is one significant area where the new code path lags behind and
that is in AVX-512 support. However, there was *extremely little*
support for that already and so this isn't a significant step backwards
and the new framework will probably make it easier to implement lowering
that uses the full power of AVX-512's table-based shuffle+blend (IMO).

Many thanks to Quentin, Andrea, Robert, and others for benchmarking
assistance. Thanks to Adam and others for help with AVX-512. Thanks to
Hal, Eric, and *many* others for answering my incessant questions about
how the backend actually works. =]

I will leave the old code path in the tree until the 3 PRs above are at
least resolved to folks' satisfaction. Then I will rip it (and 1000s of
lines of code) out. =] I don't expect this flag to stay around for very
long. It may not survive next week.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219046 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-04 03:52:55 +00:00
Chandler Carruth
2ce5aac548 [x86] Cleanup and generate precise FileCheck assertions for a bunch of
SSE tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218947 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-03 01:37:58 +00:00
Benjamin Kramer
b31a977c9c X86: Make sure that we have SSE4.1 before we generate insertps nodes.
PR19721.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208552 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 13:12:08 +00:00
Filipe Cabecinhas
e4a3254c02 Optimize shufflevector that copies an i64/f64 and zeros the rest.
Summary:
Also ran clang-format on the function. The code added is the last else
if block.

Reviewers: nadav, craig.topper, delena

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3518

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208372 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 23:16:08 +00:00
Filipe Cabecinhas
75ea413a1b Revert "Optimize shufflevector that copies an i64/f64 and zeros the rest."
This reverts commit 207992. I misread the phab number on the LGTM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207993 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 19:40:36 +00:00
Filipe Cabecinhas
a0fa9eb606 Optimize shufflevector that copies an i64/f64 and zeros the rest.
Summary:
Also ran clang-format on the function. The code added is the last else
if block.

Reviewers: nadav, craig.topper

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3518

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207992 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 19:36:28 +00:00
Nico Rieck
3c1dc3cac8 Fix non-deterministic SDNodeOrder-dependent codegen
Reset SelectionDAGBuilder's SDNodeOrder to ensure deterministic code
generation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199050 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-12 14:09:17 +00:00
Andrew Trick
6a7770b7ae Enable MI Sched for x86.
This changes the SelectionDAG scheduling preference to source
order. Soon, the SelectionDAG scheduler can be bypassed saving
a nice chunk of compile time.

Performance differences that result from this change are often a
consequence of register coalescing. The register coalescer is far from
perfect. Bugs can be filed for deficiencies.

On x86 SandyBridge/Haswell, the source order schedule is often
preserved, particularly for small blocks.

Register pressure is generally improved over the SD scheduler's ILP
mode. However, we are still able to handle large blocks that require
latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also
attempts to discover the critical path in single-block loops and
adjust heuristics accordingly.

The MI scheduler relies on the new machine model. This is currently
unimplemented for AVX, so we may not be generating the best code yet.

Unit tests are updated so they don't depend on SD scheduling heuristics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 23:33:07 +00:00
Stephen Lin
b4dc0233c9 Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion.
This was done with the following sed invocation to catch label lines demarking function boundaries:
    sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll
which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-13 20:38:47 +00:00
Andrew Trick
b2b5dc642c Revert "Temporarily enable MI-Sched on X86."
This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184823 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 02:48:58 +00:00
Andrew Trick
98a9b72e8c Temporarily enable MI-Sched on X86.
Sorry for the unit test churn. I'll try to make the change permanently
next time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184705 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 09:13:20 +00:00
Evan Cheng
623a7e146b Use a bigger hammer to fix PR11314 by disabling the "forcing two-address
instruction lower optimization" in the pre-RA scheduler.

The optimization, rather the hack, was done before MI use-list was available.
Now we should be able to implement it in a better way, perhaps in the
two-address pass until a MI scheduler is available.

Now that the scheduler has to backtrack to handle call sequences. Adding
artificial scheduling constraints is just not safe. Furthermore, the hack
is not taking all the other scheduling decisions into consideration so it's just
as likely to pessimize code. So I view disabling this optimization goodness
regardless of PR11314.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144267 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 07:43:16 +00:00
Jakob Stoklund Olesen
b26c7727c9 Kill and collapse outstanding DomainValues.
DomainValues that are only used by "don't care" instructions are now
collapsed to the first possible execution domain after all basic blocks
have been processed.  This typically means the PS domain on x86.

For example, the vsel_i64 and vsel_double functions in sse2-blend.ll are
completely collapsed to the PS domain instead of containing a mix of
execution domains created by isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144037 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 23:08:21 +00:00
Jakob Stoklund Olesen
3e5d5c53a0 Expand V_SET0 to xorps by default.
The xorps instruction is smaller than pxor, so prefer that encoding.

The ExecutionDepsFix pass will switch the encoding to pxor and xorpd
when appropriate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143996 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 19:15:58 +00:00
Jakob Stoklund Olesen
b0e47cdf3d Fix register-dependent X86 tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128867 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 00:32:44 +00:00
Chris Lattner
593051b4e2 fix PR9210 by implementing some type legalization logic for
vector fp conversions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125482 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-14 06:30:45 +00:00
Chris Lattner
ccea167db5 fix a missing shuffle pattern, PR9009. Patch by Artiom Myaskouvskey!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24 03:42:46 +00:00
Chris Lattner
c010e61ae1 fix PR8900, a shuffle miscompilation. Patch by Nadav Rotem!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-05 22:28:46 +00:00
Chris Lattner
82457d08f9 merge a bunch of shuffle tests into sse2.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112398 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 03:19:04 +00:00
Evan Cheng
bdc652bab8 Turning off post-ra scheduling for x86. It isn't a consistent win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98810 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 06:55:42 +00:00
Dan Gohman
d84ea47b89 Don't enable the post-RA scheduler on x86 except at -O3. In its
current form, it is too expensive in compile time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90781 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-07 19:04:31 +00:00
Evan Cheng
b6c215b63f Update tests for 84931.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84932 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-23 05:58:34 +00:00
David Goodwin
4c3715c2e5 Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 23:19:17 +00:00
Evan Cheng
d36076e4a3 Turn on post-alloc scheduling for x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84431 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-18 19:57:27 +00:00
Dan Gohman
36a0947820 Eliminate more uses of llvm-as and llvm-dis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81290 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-08 23:54:48 +00:00
Eli Friedman
51fe650c58 Fix test on Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79140 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15 21:28:17 +00:00
Chris Lattner
5dafafdeb4 implement support for CHECK-NEXT: in filecheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79123 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15 18:32:21 +00:00
Chris Lattner
d8d7335f79 convert to filecheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79117 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15 17:28:09 +00:00
Chris Lattner
11ade72cda rename this test to sse2.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79116 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15 17:24:09 +00:00