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7925ed05d0
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1596 Commits

Author SHA1 Message Date
Dan Gohman
7925ed05d0 Add support for multiple return values for the PPC target by 
converting call result lowering to use the CallingConvLowering
infastructure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48552 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-19 21:39:28 +00:00
Christopher Lamb
15cbde3cf6 Fix X86's isTruncateFree to not claim that truncate to i1 is free. This fixes Bill's testcase that failed for r48491. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48542 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-19 08:30:06 +00:00
Evan Cheng
82a6d23700 Fixed a coalescer bug caused by a typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48526 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-19 02:26:36 +00:00
Evan Cheng
94202018c5 Fix live variables issues: 
1. If part of a register is re-defined, an implicit kill and an implicit def are added to denote read / mod / write. However, this should only be necessary if the register is actually read later. This is a performance issue.
2. If a sub-register is being defined, and it doesn't have a previous use, do not add a implicit kill to the last use of a super-register:
   = EAX, AX<imp-use,kill>
...
AX =
In this case, EAX is live but AX is killed, this is wrong and will cause the coalescer to do bad things.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48521 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-19 00:52:20 +00:00
Evan Cheng
586ccac4ec Fix a x86-64 isel lowering bug that's been around forever. A x86-64 varargs function implicitly reads X86::AL, don't clobber it! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48515 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-18 23:36:35 +00:00
Bill Wendling
dbfd894561 It might be nice to have this run as x86 on non-x86 platforms... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48511 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-18 22:38:22 +00:00
Bill Wendling
2974e49019 Temporarily revert r48491. It's breaking test/CodeGen/X86/xorl.ll. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48510 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-18 22:29:51 +00:00
Dale Johannesen
cf49819877 Make conversions of i8/i16 to ppcf128 work. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48493 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-18 17:28:38 +00:00
Christopher Lamb
981576c818 Target independent DAG transform to use truncate for field extraction + sign extend on targets where this is profitable. Passes nightly on x86-64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48491 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-18 16:46:39 +00:00
Evan Cheng
3c88d742d4 Rewrite code that propagate isDead information after a dead copy is coalesced. This remove some ugly spaghetti code and fixed a number of subtle bugs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48490 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-18 08:26:47 +00:00
Chris Lattner
9493268124 ensure we continue matching x86-64 rotates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48437 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-17 01:35:03 +00:00
Evan Cheng
c17ba8a28d Fix PR2138. Apparently any modification to a std::multimap (including remove entries for a different key) can invalidate multimap iterators. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48371 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-14 20:44:01 +00:00
Dan Gohman
002e5d0a17 More APInt-ification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48344 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-13 22:13:53 +00:00
Evan Cheng
a56516ee08 New test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48338 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-13 08:05:02 +00:00
Evan Cheng
d99464d647 A test case I forgot to check in. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48335 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-13 06:42:46 +00:00
Evan Cheng
875357d213 TwoAddressInstructionPass enhancement. After it converts a two address instruction into a 3-address one, sink it past the instruction that kills the read-mod-write register if its definition is used past the kill. This reduces the number of live register by one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48333 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-13 06:37:55 +00:00
Evan Cheng
9e23336d0c Experimental scheduler change to schedule / coalesce the copies added for function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted: 
entry: 0x12049d0, LLVM BB @0x1201fd0, ID#0:
Live Ins: %EAX %EDX %ECX
        %reg1031<def> = MOVPC32r 0
        %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
        %reg1028<def> = MOV32rr %EAX
        %reg1029<def> = MOV32rr %EDX
        %reg1030<def> = MOV32rr %ECX
        %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x1201910 + 0]
        %reg1025<def> = MOV32rr %reg1029
        %reg1026<def> = MOV32rr %reg1030
        %reg1024<def> = MOV32rr %reg1028

The copies unnecessarily increase register pressure and it will end up requiring a physical register to be spilled.

With -schedule-livein-copies:
entry: 0x12049d0, LLVM BB @0x1201fa0, ID#0:
Live Ins: %EAX %EDX %ECX
        %reg1031<def> = MOVPC32r 0
        %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
        %reg1024<def> = MOV32rr %EAX
        %reg1025<def> = MOV32rr %EDX
        %reg1026<def> = MOV32rr %ECX
        %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x12018e0 + 0]

Much better!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48307 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 22:19:41 +00:00
Dan Gohman
89964b4ca1 Fix this test on hosts that don't have sse2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48296 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 20:40:51 +00:00
Dan Gohman
38459f01c0 Make this test x86-specific for now; targets that don't use 
the automated CallingConv code to handle return values typically
don't support multiple return values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48265 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-12 00:25:14 +00:00
Dan Gohman
cb5b317890 Basic feature test for multiple return values in codegen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48260 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 23:53:16 +00:00
Anton Korobeynikov
f1765e8298 Testcase for PR2137 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48258 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 22:43:42 +00:00
Anton Korobeynikov
0fb2033f91 Update testcase for recent aliases change 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48250 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 21:42:20 +00:00
Dan Gohman
6a6d27ac0b Add a test to ensure that all-ones vectors are materialized with pcmpeqd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48247 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 21:37:00 +00:00
Dan Gohman
9736028d84 Use the correct value for InSignBit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48245 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 21:29:43 +00:00
Chris Lattner
e12ecf272d Implement basic support for the 'f' register class constraint. This basically 
works, but probably won't if you mix it with 't' or 'u' yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48243 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 19:50:13 +00:00
Dale Johannesen
01c18a7275 The feature this is testing did not work in the general case, 
and has been removed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48232 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 17:48:26 +00:00
Evan Cheng
9a8094159d Learn how to xfail a test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48219 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 07:51:31 +00:00
Evan Cheng
676dd7c80b When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48218 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 07:19:34 +00:00
Evan Cheng
de13acf862 XFAIL due to Dale's change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48216 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 07:15:44 +00:00
Dan Gohman
034f60ed24 Generalize ExpandIntToFP to handle the case where the operand is legal 
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48206 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-11 01:59:03 +00:00
Scott Michel
405fba12ce - Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency. 
- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48197 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 23:49:09 +00:00
Chris Lattner
03fdec04d1 Don't emit FP_REG_KILL into a block that just returns. Nothing 
can be live out of the block anyway, so it isn't needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48192 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 23:34:12 +00:00
Dan Gohman
a2e9485e34 Implement more support for fp-to-i128 and i128-to-fp conversions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48189 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 23:03:31 +00:00
Bill Wendling
2b65c4e7cc Update llc flags for PPC register scavenger. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48187 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 22:59:08 +00:00
Dan Gohman
76c605b18e Fix mul expansion to check the correct number of bits for 
zero extension when checking if an unsigned multiply is
safe.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48171 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 20:42:19 +00:00
Dale Johannesen
45bcbf491c These tests don't work unless SSE2 is active. 
Judging from the checking comments this is intentional,
so add the flag (makes them pass on non-x86 host).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48157 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 17:33:57 +00:00
Dale Johannesen
ca765303fb There is no "-mattr=+sse1" flag; fix test for non-x86 hosts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48156 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 17:13:37 +00:00
Scott Michel
78c47fa50b Integer comparison tests for CellSPU. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48152 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 16:58:52 +00:00
Evan Cheng
4ff3f1cc57 - Fix a subtle bug in RemoveCopyByCommutingDef. ALR is the live range where the source is defined; BLR is the live range which is defined by the copy. 
If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.                                                                                                 
 A = or A, B                                                                                                                                                            
 ...                                                                                                                                                                    
 B = A                                                                                                                                                                  
 ...                                                                                                                                                                    
 C = A<kill>                                                                                                                                                            
 ...                                                                                                                                                                    
   = B                                                                                                                                                                  
                                                                                                                                                                        
then do not add kills of A to the newly created B interval.
- Also fix some kill info update bug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48141 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 08:11:32 +00:00
Evan Cheng
f79e60649a Avoid creating BUILD_VECTOR of all zero elements of "non-normalized" type (e.g. v8i16 on x86) after legalizer. Instruction selection does not expect to see them. In all likelihood this can only be an issue in a bugpoint reduced test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48136 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 07:19:13 +00:00
Chris Lattner
8d88dbcbae remove an execution test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48135 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-10 06:53:14 +00:00
Evan Cheng
7a0690d1b6 Fix RUN line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48116 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 19:55:22 +00:00
Chris Lattner
f30e1cf9b7 teach X86InstrInfo::copyRegToReg how to copy into ST(0) from 
an RFP register class.

Teach ScheduleDAG how to handle CopyToReg with different src/dst 
reg classes.

This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48107 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 09:15:31 +00:00
Chris Lattner
02b6d25a27 Add ScheduleDAG support for copytoreg where the src/dst register are 
in different register classes, e.g. copy of ST(0) to RFP*.  This gets
some really trivial inline asm working that plops things on the top of
stack (PR879)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48105 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 08:49:15 +00:00
Tanya Lattner
76806b6a43 Remove llvm-upgrade and update tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48103 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 08:16:40 +00:00
Chris Lattner
ce6e492997 reduce this testcase more 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48092 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 06:57:21 +00:00
Chris Lattner
67f453aae7 Finish implementing a readme entry: when inserting an i64 variable 
into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle.  This allows us to compile
vec_set-B.ll into:

_test3:
	movl	$1234567, %eax
	andl	4(%esp), %eax
	movd	%eax, %xmm0
	ret

instead of:

_test3:
	subl	$28, %esp
	movl	$1234567, %eax
	andl	32(%esp), %eax
	movl	%eax, (%esp)
	movl	$0, 4(%esp)
	movq	(%esp), %xmm0
	addl	$28, %esp
	ret



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48090 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 05:42:06 +00:00
Chris Lattner
62098040a1 Implement a readme entry, compiling 
#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}

into:
	movl	$1, %eax
	movd	%eax, %xmm0
	ret

instead of a constant pool load.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48063 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 01:05:04 +00:00
Chris Lattner
8aca4b13a8 upgrade this test 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48062 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 00:32:10 +00:00
Chris Lattner
da8de316a8 make this test harder 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48061 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-09 00:30:06 +00:00