Evan Cheng
7a42b08be8
Should be using Bcc (average) latency to determine if-conversion threshold, not BL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73759 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 06:56:26 +00:00
Evan Cheng
974fe5d691
Transfer dead markers when a ldrd is changed into a ldm or a pair of ldr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73749 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 01:59:04 +00:00
Evan Cheng
8557c2bcb8
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73747 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 01:51:50 +00:00
Eli Friedman
6b7bb42c36
Mark a few Thumb instructions commutable; just happened to spot this
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while experimenting. I'm reasonably sure this is correct, but please
tell me if these instructions have some strange property which makes this
change unsafe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73746 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 01:43:08 +00:00
Chris Lattner
4e0f25b603
merge the common darwin settings from the X86/PPC/ARM targets
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into DarwinTargetAsmInfo.cpp. The remaining differences should
be evaluated. It seems strange that x86/arm has .zerofill but ppc
doesn't, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73742 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 00:08:39 +00:00
Chris Lattner
a93ca92379
move mangler quote handling from asm printers to TargetAsmInfo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73738 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 23:41:35 +00:00
Chris Lattner
b839c3f577
simplify macro debug info directive handling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73736 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 23:31:37 +00:00
Evan Cheng
cd828618b8
Remove UseThumbBacktraces. Just check if subtarget is darwin.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 23:14:30 +00:00
Evan Cheng
b13bafe5c1
On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73720 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 20:37:15 +00:00
Evan Cheng
f9f1da17f8
- Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints.
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- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73671 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 02:04:01 +00:00
Bob Wilson
ff6de36558
ARM unified syntax is not specific to ELF; use it for Darwin, too.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73665 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 00:36:17 +00:00
Anton Korobeynikov
7c4f7dd43a
Fix asm string from MOVi16
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73661 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 23:43:36 +00:00
Anton Korobeynikov
d61eca5330
Thumb2 instructions are enabled only in unified assembler mode.
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Emit switch directive for it. I have no idea whether this is
requirement for Darwin or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73660 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 23:43:18 +00:00
Anton Korobeynikov
52237119a9
Initial support for some Thumb2 instructions.
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Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73622 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 18:13:58 +00:00
Douglas Gregor
1555a23335
Introduce new headers whose inclusion forces linking and
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initialization of all targets (InitializeAllTargets.h) or assembler
printers (InitializeAllAsmPrinters.h). This is a step toward the
elimination of relinked object files, so that we can build normal
archives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73543 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 20:12:29 +00:00
Anton Korobeynikov
385f5a99ec
Address review comments: add 3 ARM calling conventions.
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Dispatch C calling conv. to one of these conventions based on
target triple and subtarget features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73530 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 18:50:49 +00:00
Anton Korobeynikov
2932795309
GNU as refuses to assemble "pop {}" instruction. Do not emit such
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(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73529 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16 18:49:08 +00:00
Evan Cheng
88cc7c4194
On Darwin, frame pointer r7 is never available.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73434 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 22:32:01 +00:00
Anton Korobeynikov
bb62962342
Rename methods for the sake of consistency.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73428 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 21:46:20 +00:00
Evan Cheng
675860758e
Typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73422 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 21:18:20 +00:00
Evan Cheng
d780f35794
Do not form ldrd / strd if the two dests / srcs are the same. Code clean up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73413 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 20:54:56 +00:00
Evan Cheng
7f04428738
Silence a warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73406 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 19:36:32 +00:00
Evan Cheng
358dec5180
Part 1.
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- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 08:28:29 +00:00
Evan Cheng
e7d6df7353
Add a ARM specific pre-allocation pass that re-schedule loads / stores from
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consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.
This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-13 09:12:55 +00:00
Evan Cheng
cd799b99cb
Mark some pattern-less instructions as neverHasSideEffects.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73252 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-12 20:46:18 +00:00
Anton Korobeynikov
2e7ccfce98
Typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73098 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 22:59:50 +00:00
Anton Korobeynikov
dada95b5b3
Revert hunk commited by accident
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73097 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 22:57:18 +00:00
Anton Korobeynikov
0eebf653a7
The attached patches implement most of the ARM AAPCS-VFP hard float
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ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.
Patch by Sandeep Patel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73095 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 22:53:56 +00:00
Anton Korobeynikov
fbbf1eeccf
Separate V6 from V6T2 since the latter has some extra nice instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73085 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 21:20:36 +00:00
Anton Korobeynikov
a7b0ded2a2
Add helper for checking of Thumb1 mode
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73080 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 20:31:02 +00:00
Dan Gohman
2392efef1b
Add explicit keywords.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72969 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 23:05:51 +00:00
Evan Cheng
925492279a
Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72955 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 19:08:58 +00:00
Evan Cheng
87d59e49e9
When merging multiple load / store instructions. Use the DebugLoc of the first one.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72952 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 18:19:23 +00:00
Evan Cheng
5ba71887f9
Code clean up: return vector by reference rather than by value. No functionality changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72950 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 17:56:14 +00:00
Dan Gohman
c965ee223c
Remove some unnecessary #includes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72948 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 16:32:58 +00:00
Evan Cheng
1488326156
Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72826 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 01:15:28 +00:00
Evan Cheng
70fd60bd57
Temporarily revert 72756 for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72757 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03 07:40:47 +00:00
Evan Cheng
9d5fb981b0
Fold preceding / trailing base inc / dec into the single load / store as well.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72756 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03 06:14:58 +00:00
Anton Korobeynikov
70459bef9c
Implement review feedback. Make thumb2 'normal' subtarget feature
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72698 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-01 20:00:48 +00:00
Bruno Cardoso Lopes
434dd4fd94
Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron Gray
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72697 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-01 19:57:37 +00:00
Anton Korobeynikov
d260c248ab
Do not emit "generic" CPU string. This fixes PR4291.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72696 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-01 19:03:17 +00:00
Bruno Cardoso Lopes
a3f99f9033
First patch in the direction of splitting MachineCodeEmitter in two subclasses:
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JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72631 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-30 20:51:52 +00:00
Bill Wendling
51b16f4737
Untabification.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72604 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-30 01:09:53 +00:00
Anton Korobeynikov
d4022c3fbb
Add placeholder for thumb2 stuff
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72593 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-29 23:41:08 +00:00
Chris Lattner
0c85aabfdc
fix typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72395 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-25 19:51:07 +00:00
Anton Korobeynikov
6d7d2aa38a
Add ARMv7 architecture, Cortex processors and different FPU modes handling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72337 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-23 19:51:43 +00:00
Anton Korobeynikov
88ce667003
Emit ARM Build Attributes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72336 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-23 19:51:20 +00:00
Anton Korobeynikov
41a024385f
Propagate CPU string out of SubtargetFeatures
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-23 19:50:50 +00:00
Bob Wilson
2f95461ee2
Only 64-bit targets support TImode libcalls. Disable the TImode shift libcalls
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for ARM. This fixes rdar://6908807.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72269 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-22 17:38:41 +00:00
Bob Wilson
261f2a2337
Minor formatting fixes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72172 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-20 16:30:25 +00:00