Commit Graph

2753 Commits

Author SHA1 Message Date
Owen Anderson
d5d81a457b Oops, I accidentally broke the fallback case with my last commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55704 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03 17:51:57 +00:00
Owen Anderson
99aaf108cd Fix an issue where we were reusing materializations of constants in blocks not dominated by the materialization. This is
the simple fix, materializing the constant before every use.  It might be better to either track domination of uses or
to materialize all constants and the beginning of the function and let remat sort when to do materialization at uses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55703 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03 17:37:03 +00:00
Dan Gohman
f0cbcd4880 Split the SelectionDAG-building code, including the FunctionLoweringInfo
and SelectionDAGLowering classes, out of SelectionDAGISel.cpp and put
it in a separate file, SelectionDAGBuild.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55701 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03 16:12:24 +00:00
Dan Gohman
94b8d7ea63 Separate MachineInstr-emitting routines from actual scheduling
routines and move them into a separate file, ScheduleDAGEmit.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55699 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03 16:01:59 +00:00
Evan Cheng
f45261fb9b If TargetSelectInstruction returns true, move to next instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55692 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03 06:43:41 +00:00
Evan Cheng
36fd941fc0 80 col violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55668 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-02 21:59:13 +00:00
Dan Gohman
d2ff647964 Ensure that HandlePHINodesInSuccessorBlocks is run for all blocks,
even in FastISel mode in the case where FastISel successfully 
selects all the instructions. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55641 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-02 20:17:56 +00:00
Gabor Greif
ed63214fcb Provide two overloads of AnalyzeNewNode.
The first can update the SDNode in an SDValue
while the second is called with SDNode* and
returns a possibly updated SDNode*.

This patch has no intended functional impact,
but helps eliminating ugly temporary SDValues.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55608 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 15:10:19 +00:00
Duncan Sands
1189f3ac3b Even though no caller actually uses the new value
(what matters is that it is added to the worklist),
it seems more logical to return it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55606 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 13:11:13 +00:00
Bill Wendling
2692d59574 Another situation where ROTR is cheaper than ROTL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55577 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31 01:13:31 +00:00
Bill Wendling
353dea2f0a For this pattern, ROTR is the cheaper option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55576 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31 01:04:56 +00:00
Bill Wendling
c5cbda12e9 - Fix comment so that it describes how the code really works:
// fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
   //   (rotl x, y)
   // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
   //   (rotr x, (sub 32, y))

Example: (x == 0xDEADBEEF and y == 4)

    (x << 4) | (x >> 28)
 => 0xEADBEEF0 | 0x0000000D
 => 0xEADBEEFD

    (rotl x, 4)
 => 0xEADBEEFD

    (rotr x, 28)
 => 0xEADBEEFD

- Fix comment and code for second version. It wasn't using the rot* propertly.

   // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 
   //   (rotr x, y)
   // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
   //   (rotl x, (sub 32, y))

    (x << 28) | (x >> 4)
 => 0xD0000000 | 0x0DEADBEE
 => 0xDDEADBEE

    (rotl x, 4)
 => 0xEADBEEFD

    (rotr x, 28)
 => (0xEADBEEFD)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55575 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31 00:37:27 +00:00
Gabor Greif
dc71563794 typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55574 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30 22:16:05 +00:00
Gabor Greif
12632d2222 fix some 80-col violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55571 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30 19:29:20 +00:00
Evan Cheng
eb9f89287e Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55558 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30 02:03:58 +00:00
Owen Anderson
cc54e76cc6 Fix an issue where a use might be selected before a def, and then we didn't respect the pre-chosen vreg
assignment when selecting the def.  This is the naive solution to the problem: insert a copy to the pre-chosen
vreg.  Other solutions might be preferable, such as:
  1) Passing the dest reg into FastEmit_.  However, this would require the higher level code to know about reg classes, which they don't currently.
  2) Selecting blocks in reverse postorder.  This has some compile time cost for computing the order, and we'd need to measure its impact.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55555 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30 00:38:46 +00:00
Evan Cheng
4529966d99 Fix 80 col. violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55551 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 23:20:46 +00:00
Evan Cheng
17a568b668 Back out 55498. It broken Apple style bootstrapping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55549 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 22:21:44 +00:00
Dan Gohman
99b218218c Add a target callback for FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55512 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 23:21:34 +00:00
Gabor Greif
ba36cb5242 erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 21:40:38 +00:00
Dan Gohman
205d92589b Implement null and undef values for FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55500 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 21:19:07 +00:00
Dan Gohman
a3f8b7a4ce Optimize DAGCombiner's worklist processing. Previously it started
its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.

This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55498 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 21:01:56 +00:00
Dan Gohman
9ffd8b5720 Move CaseBlock, JumpTable, and BitTestBlock to be members of
SelectionDAGLowering instead of being in an anonymous namespace.
This fixes warnings about SelectionDAGLowering having fields
using anonymous namespaces.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55497 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 20:38:18 +00:00
Dan Gohman
5edd361497 Fix a FastISel bug where the instructions from lowering the arguments
were being emitted after the first instructions of the entry block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55496 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 20:28:56 +00:00
Rafael Espindola
91ee5454ae Reduce the size of the Parts vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55483 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 18:29:58 +00:00
Owen Anderson
c0bb68b982 Hook up support for fast-isel of trunc instructions, using the newly working support for EXTRACT_SUBREG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55482 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 18:26:01 +00:00
Owen Anderson
40a468f249 FastEmitInst_extractsubreg doesn't need to be passed the register class. It can get it from MachineRegisterInfo instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55476 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 17:47:37 +00:00
Rafael Espindola
c748ffa4e4 Correctly resize the Parts array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55471 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 14:24:45 +00:00
Dale Johannesen
e00a8a2a2e Split the ATOMIC NodeType's to include the size, e.g.
ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.

This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad.  This is the alternative.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55457 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 02:44:49 +00:00
Dan Gohman
7c3234c6be Reorganize the lifetimes of the major objects SelectionDAGISel
works with.

SelectionDAG, FunctionLoweringInfo, and SelectionDAGLowering
objects now get created once per SelectionDAGISel instance, and
can be reused across blocks and across functions. Previously,
they were created and destroyed each time they were needed.

This reorganization simplifies the handling of PHI nodes, and
also SwitchCases, JumpTables, and BitTestBlocks. This
simplification has the side effect of fixing a bug in FastISel
where successor PHI nodes weren't being updated correctly.

This is also a step towards making the transition from FastISel
into and out of SelectionDAG faster, and also making
plain SelectionDAG faster on code with lots of little blocks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55450 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-27 23:52:12 +00:00
Owen Anderson
8970f00def Add a helper method that will be used to support EXTRACT_SUBREG for selecting trunc's in fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55439 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-27 22:30:02 +00:00
Dan Gohman
a318dabc0e Fix FastISel's bitcast code for the case where getRegForValue fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55431 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-27 20:41:38 +00:00
Owen Anderson
6336b70541 Use TargetLowering to get the types in fast isel, which handles pointer types correctly for our purposes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55428 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-27 18:58:30 +00:00
Dan Gohman
151ed61a2f Don't check TLI.getOperationAction. The FastISel way is to
just try to do the action and let the tablegen-generated code
determine if there is target-support for an operation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55427 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-27 18:15:05 +00:00
Dan Gohman
ad368ac2b5 Add a new FastISel method, getRegForValue, which takes care of
the details of materializing constants and other values into
registers, and make use of it in several places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55426 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-27 18:10:19 +00:00
Dan Gohman
96a9999d79 Add a comment about the current floating-point constant code in FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55425 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-27 18:01:42 +00:00
Dan Gohman
e5a8dc5cc4 Optimize ScheduleDAGRRList's topological sort to use one pass instead
of two, and to not need a scratch std::vector. Also, compute the ordering
immediately in the result array, instead of in another scratch std::vector
that is copied to the result array.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55421 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-27 16:29:48 +00:00
Dan Gohman
3a09d891a4 Optimize ScheduleDAG's ComputeDepths and ComputeHeights to not need
a scratch std::vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55420 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-27 16:27:25 +00:00
Dan Gohman
10df0fa73e Basic FastISel support for floating-point constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55401 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-27 01:09:54 +00:00
Owen Anderson
96c5ea878c Fix handling of inttoptr and ptrtoint when unhandled operands are present.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55400 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-27 00:35:37 +00:00
Owen Anderson
9d5b416240 Add support for fast isel of inttoptr and ptrtoint in the cases where truncation is not needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55399 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-27 00:31:01 +00:00
Owen Anderson
d0533c9998 Factor out a large amoutn of the cast handling code in fast isel into helper methods.
This simultaneously makes the code simpler and adds support for sext as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55398 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26 23:46:32 +00:00
Owen Anderson
97e2568f46 Add support for fast isel of zext.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55396 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26 23:14:49 +00:00
Gabor Greif
99a6cb92d1 disallow direct access to SDValue::ResNo, provide a getter instead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55394 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26 22:36:50 +00:00
Owen Anderson
13269335a5 Add support for fptosi of constants in fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55393 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26 22:34:28 +00:00
Dan Gohman
3200d92947 Optimize SelectionDAG's topological sort to use one pass instead
of two, and to not need a scratch std::vector. Also, use the
SelectionDAG's topological sort in LegalizeDAG instead of having
a separate implementation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55389 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26 21:42:18 +00:00
Dan Gohman
763d89343b Refactor the bitcast code into its own function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55387 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26 21:28:54 +00:00
Dan Gohman
80bc6e2243 Make FastISel use the correct argument type when casting GEP indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55384 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26 20:57:08 +00:00
Dan Gohman
b71fea248f Don't select binary instructions with illegal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55383 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26 20:52:40 +00:00
Owen Anderson
a843b8d391 Add support for fast isel of sitofp, and remove some unnecessary and imprecise legality checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55381 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26 20:37:00 +00:00