R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123294 91177308-0d34-0410-b5e6-96231b3b80d8
Added test to check bl __aeabi_read_tp gets emitted properly for ELF/ASM
as well as ELF/OBJ (including fixup)
Also added support for ELF::R_ARM_TLS_IE32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121312 91177308-0d34-0410-b5e6-96231b3b80d8
actuall addresses in a .o file, so it is better to let the MachO writer compute
it.
This is good for two reasons. First, areas that shouldn't care about
addresses now don't have access to it. Second, the layout of each section
is independent. I should use this in a subsequent commit to speed it up.
Most of the patch is just removing the section address computation. The two
interesting parts are the change on how we handle padding in the end
of sections and how MachO can get the address of a-b when a and b are in
different sections.
Since now the expression evaluation normally doesn't know the section address,
it will think that a-b needs relocation and let the MachO writer know. Once
it has computed the section addresses, it calls back the expression evaluation
with the section addresses to resolve these expressions.
The remaining problem is the handling of padding. Currently it will create
a special alignment fragment at the end. Since that fragment doesn't update
the alignment of the section, it needs the real address to be computed.
Since now the layout will not compute a-b with a and b in different sections,
the only effect that the special alignment fragment has is update the
address size of the section. This can also be done by the MachO writer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121076 91177308-0d34-0410-b5e6-96231b3b80d8
+ ARM/X86/MBlaze now share a common RecordRelocation
+ ARM/X86/MBlaze arch specific routines are limited to GetRelocType()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121043 91177308-0d34-0410-b5e6-96231b3b80d8
contain only data. Handle them specially instead of using AddSectionToTheEnd.
This moves a hack from the generic assembler to the elf writer. It is also
a bit faster and should make other improvements easier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120683 91177308-0d34-0410-b5e6-96231b3b80d8
Lifted adjustFixupValue() from Darwin for sharing w ELF.
Test added
TODO:
refactor ELFObjectWriter::RecordRelocation more.
Possibly share more code with Darwin?
Lots more relocations...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120534 91177308-0d34-0410-b5e6-96231b3b80d8
Next step is to rationally break apart the RecordRelocation()
Probably the step will be to have 1 member function for ech slot of the ELFRelocationEntry()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119978 91177308-0d34-0410-b5e6-96231b3b80d8
variable if recursing fails to simplify it.
Factor AliasedSymbol to be a method of MCSymbol.
Update MCAssembler::EvaluateFixup to match the change in
EvaluateAsRelocatableImpl.
Remove the WeakRefExpr hack, as the object writer now sees the weakref with
no extra effort needed.
Nothing else is using MCTargetExpr, but keep it for now.
Now that the ELF writer sees relocations with aliases, handle
.weak foo2
foo2:
.weak bar2
.set bar2,foo2
.quad bar2
the same way gas does and produce a relocation with bar2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119152 91177308-0d34-0410-b5e6-96231b3b80d8
Added 2 new subclasses - X86ELFObjectWriter and ARMELFObectWriter.
ARM and X86 require different code for RecordRelocation(), possibly others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119149 91177308-0d34-0410-b5e6-96231b3b80d8
