Commit Graph

15285 Commits

Author SHA1 Message Date
Nick Lewycky
8369687576 Make some intrinsics safe to speculatively execute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147036 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 05:52:02 +00:00
Evan Cheng
1e33e8b715 Fix a couple of copy-n-paste bugs. Noticed by George Russell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147032 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 03:04:10 +00:00
Jim Grosbach
3471d4fbbd ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 00:38:54 +00:00
Akira Hatanaka
c7541c49a9 Fix bug in zero-store peephole pattern reported in pr11615.
The patch and test case were originally written by Mans Rullgard.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 00:31:10 +00:00
Akira Hatanaka
c79507a4dd Expand 64-bit CTLZ nodes if target architecture does not support it. Add test
case for DCLO and DCLZ.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 00:20:27 +00:00
Akira Hatanaka
cf966cb0c3 Test case for r147017.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147018 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:58:36 +00:00
Jim Grosbach
06d738c76a Enable and fix a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147011 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:20:00 +00:00
Akira Hatanaka
2fd0475cdb Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147008 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:10:57 +00:00
Akira Hatanaka
8dc684d2a2 64-bit data directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:52:19 +00:00
Akira Hatanaka
ef43c2de86 32-to-64-bit sext_inreg pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:40:40 +00:00
Akira Hatanaka
990d639f55 Add code in MipsDAGToDAGISel for selecting constant +0.0.
MIPS64 can generate constant +0.0 with a single DMTC1 instruction. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146999 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:25:50 +00:00
Jakob Stoklund Olesen
52346e964f Heed spill slot alignment on ARM.
Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.

Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack.  Don't use aligned spill code in that case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:15:04 +00:00
Jim Grosbach
5b484312c6 ARM assembly parsing and encoding for VST2 single-element, double spaced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 20:46:29 +00:00
Jim Grosbach
514806b52e ARM enable a few more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146985 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 20:03:00 +00:00
Jim Grosbach
95fad1c603 ARM assembly parsing and encoding for VLD2 single-element, double spaced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 19:21:26 +00:00
Evan Cheng
afff941211 ARM target code clean up. Check for iOS, not Darwin where it makes sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 18:26:50 +00:00
Elena Demikhovsky
ba4f83b4e9 This is the second fix related to VZEXT_MOVL node.
The failure that I see in the current version is:

LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
  0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
    0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
      0x18b9870: v4i64 = undef [ID=4]
      0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
        0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
      0x18b9970: i32 = Constant<0> [ID=3]
    0x18b9170: v2i64 = undef [ORD=1] [ID=1]
    0x18b9570: i32 = Constant<2> [ID=5]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 13:34:28 +00:00
Chandler Carruth
f2d7693fbb Begin teaching the X86 target how to efficiently codegen patterns that
use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.

The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 11:19:37 +00:00
Andrew Trick
1885687462 Unit test for r146950: LSR postinc expansion, PR11571.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 01:43:20 +00:00
Bob Wilson
c0b0e57a87 Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.
We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers.  But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore.  Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early.  This also more accurately reflects
when the registers are clobbered.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 01:29:27 +00:00
Jim Grosbach
04b5d93250 ARM assembly shifts by zero should be plain 'mov' instructions.
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.

rdar://10604663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 00:59:38 +00:00
Chris Lattner
ea93373a0a Now that PR11464 is fixed, reapply the patch to fix PR11464,
merging types by name when we can.  We still don't guarantee type name linkage
but we do it when obviously the right thing to do.  This makes LTO type names 
easier to read, for example.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146932 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 00:12:26 +00:00
Chris Lattner
68910509fd fix PR11464 by preventing the linker from mapping two different struct types from the source module onto the same opaque destination type. An opaque type can only be resolved to one thing or another after all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146929 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 00:03:52 +00:00
Evan Cheng
26118cfaa0 Move tests to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146923 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 23:26:44 +00:00
Jim Grosbach
2f196747f1 ARM assembly parsing and encoding support for LDRD(label).
rdar://9932658

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 23:06:24 +00:00
Akira Hatanaka
59eb8056e0 Add a test case for r146900.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146901 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 20:24:28 +00:00
Akira Hatanaka
f06cb2b207 Add patterns for matching immediates whose lower 16-bit is cleared. These
patterns emit a single LUi instruction instead of a pair of LUi and ORi.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 20:21:18 +00:00
Jim Grosbach
d22170e16a ARM NEON two-operand aliases for VPADD.
rdar://10602276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:51:03 +00:00
Akira Hatanaka
ee973147ac Remove definitions of double word shift plus 32 instructions. Assembler or
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146893 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:44:09 +00:00
Akira Hatanaka
89dc8d790d Remove the restriction on the first operand of the add node in SelectAddr.
This change reduces the number of instructions generated.

For example, 
(load (add (sub $n0, $n1), (MipsLo got(s))))

results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)

Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:28:37 +00:00
Jim Grosbach
61b74b4247 ARM NEON implied destination aliases for VMAX/VMIN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 18:57:38 +00:00
Jim Grosbach
eeaf1c1636 ARM NEON relax parse time diagnostics for alignment specifiers.
There's more variation that we need to handle. Error checking will need
to be on operand predicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 18:31:43 +00:00
Joerg Sonnenberger
3470693641 Allow inlining of functions with returns_twice calls, if they have the
attribute themselve.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-18 20:35:43 +00:00
Chad Rosier
2e6119429f Revert 146728 as it's causing failures on some of the external bots as well as
internal nightly testers.  Original commit message:

By popular demand, link up types by name if they are isomorphic and one is an
autorenamed version of the other.   This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large
app.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146838 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-17 22:19:53 +00:00
Kevin Enderby
67005b311c Revert r146822 at Pete Cooper's request as it broke clang self hosting.
Hope I did this correctly :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146834 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-17 19:48:52 +00:00
Pete Cooper
93ca12299f SimplifyCFG now predicts some conditional branches to true or false depending on previous branch on same comparison operands.
For example, 

if (a == b) {
    if (a > b) // this is false
    
Fixes some of the issues on <rdar://problem/10554090>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146822 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-17 06:32:38 +00:00
Manuel Klimek
5bb210e134 Deleting the json-bench-test until I understand why it is flaky.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146821 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-17 06:29:32 +00:00
Evan Cheng
b16db81719 Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146805 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-17 01:25:34 +00:00
Rafael Espindola
8f7d12ccfd Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the
asm parsing and testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146801 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-17 01:14:52 +00:00
Lang Hames
8b99c1e42c Make sure that the lower bits on the VSELECT condition are properly set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146800 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-17 01:08:46 +00:00
Dan Gohman
ce16339930 The powers that be have decided that LLVM IR should now support 16-bit
"half precision" floating-point with a first-class type.

This patch adds basic IR support (but not codegen support).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146786 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-17 00:04:22 +00:00
Eric Christopher
2e1b0c0cd9 When recursing for the original size of a type, stop if we are at a
pointer or a reference type - we actually just want the size of the
pointer then for that.

Fixes rdar://10335756

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146785 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 23:42:45 +00:00
Jakob Stoklund Olesen
b076fb7762 Fix off-by-one error in bucket sort.
The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.

<rdar://problem/10594653>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146767 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 23:00:05 +00:00
Benjamin Kramer
903456245b Hexagon: Fix a nasty order-of-initialization bug.
Reenable the tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146750 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 19:08:59 +00:00
Manuel Klimek
76f13017fc Adds a JSON parser and a benchmark (json-bench) to catch performance regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 13:09:10 +00:00
Chris Lattner
9646acfccf By popular demand, link up types by name if they are isomorphic and one is an
autorenamed version of the other.   This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large app.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146728 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 08:36:07 +00:00
Craig Topper
94438ba538 Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 08:06:31 +00:00
Kostya Serebryany
478a4d997a [asan] add a test for instrumenting globals
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146718 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 01:28:19 +00:00
Eli Friedman
7e840efc23 Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146709 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 23:46:18 +00:00
Jim Grosbach
a738da7bd3 ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146699 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:56:33 +00:00