Eric Christopher
83e05c48de
Temporarily revert r56550 until missing commit can be added.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56551 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-24 08:30:44 +00:00
Bill Wendling
df0c7bc52d
Refactor the constant folding code into it's own function. And call it from both
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the SelectionDAG and DAGCombiner code. The only functionality change is that now
the DAG combiner is performing the constant folding for these operations instead
of being a no-op.
This is *not* in response to a bug, so there isn't a testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56550 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-24 07:11:26 +00:00
Dale Johannesen
86b49f8e2d
Next round of earlyclobber handling. Approach the
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RA problem by expanding the live interval of an
earlyclobber def back one slot. Remove
overlap-earlyclobber throughout. Remove
earlyclobber bits and their handling from
live internals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56539 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-24 01:07:17 +00:00
Dan Gohman
3d84a76917
Refactor the logic for testing if an instruction is dead into a
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separate method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56531 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-24 00:27:38 +00:00
Dan Gohman
035268eaf7
Set SetStore to false, to allow this pass to delete
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dead loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56529 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-24 00:07:08 +00:00
Dan Gohman
3e4fb70c6a
Add a method to MachineInstr for testing whether it makes
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any volatile memory references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56528 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-24 00:06:15 +00:00
Evan Cheng
da43bcf624
Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56526 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-24 00:05:32 +00:00
Devang Patel
eaf42abab6
s/ParameterAttributes/Attributes/g
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56513 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-23 23:03:40 +00:00
Dan Gohman
b2c3e3fdd9
Now that DeadMachineInstructionElim is basically working
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correctly, it's not necessary to explicitly remove registers
from their use-def lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56509 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-23 22:04:18 +00:00
Dan Gohman
d57dd5f4e6
Arrange for FastISel code to have access to the MachineModuleInfo
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object. This will be needed to support debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56508 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-23 21:53:34 +00:00
Dan Gohman
8468d1a845
Track local physical register liveness. This is not the most
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efficient implementation possible, but it's pretty simple and
good enough for the time being.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56504 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-23 21:40:44 +00:00
Dan Gohman
086ec9976f
Replace the LiveRegs SmallSet with a simple counter that keeps
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track of the number of live registers, which is all the set was
being used for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56498 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-23 18:50:48 +00:00
Owen Anderson
fae86eddeb
Add initial support for inserting last minute copies.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56485 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-23 04:37:10 +00:00
Dan Gohman
87a0f10dc7
Fix the alignment of loads from constant pool entries when the
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load address has an offset from the base of the constant pool
entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56479 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-22 22:40:08 +00:00
Evan Cheng
ef901c5756
Livestacks really does preserve everything.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56476 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-22 22:26:15 +00:00
Evan Cheng
8b56a90bec
Instead of setPreservesAll, just mark them preseving machine loop info and machine dominators.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56475 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-22 22:21:38 +00:00
Owen Anderson
e04cec0ecf
Significant improvements to the logic for merging live intervals. This code can't
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just use LI::MergeValueAsValue, as its behavior in the presence of overlapping ranges
isn't what StrongPHIElimination wants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56472 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-22 21:58:58 +00:00
Dale Johannesen
0bb41608e9
Make log, log2, log10, exp, exp2 use Expand by
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default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56471 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-22 21:57:32 +00:00
Evan Cheng
bbeeb2a61e
Mark several codegen passes as preserving all analysis.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56469 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-22 20:58:04 +00:00
Dale Johannesen
f74185b80e
More refactoring. Yawn.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56468 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-22 20:51:30 +00:00
Dale Johannesen
c4342eab9b
Refactor FP intrinisic setup. Per review feedback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56456 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-22 19:51:58 +00:00
Evan Cheng
242ebd145d
Per review feedback: Only perform
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(srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c))
etc. when both "trunc" and "and" have single uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56452 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-22 18:19:24 +00:00
Oscar Fuentes
3d01fc7de8
Initial support for the CMake build system.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56419 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-22 01:08:49 +00:00
Bill Wendling
cd4c73aa70
Add helper function to get a 32-bit floating point constant. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56418 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-22 00:44:35 +00:00
Dan Gohman
3bdf5fe71a
Factor out code into HandleVirtRegDef, for consistency with
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Handle{Virt,Phys}Reg{Def,Use}. Remove a redundant check
for register zero, and redundant checks for isPhysicalRegister.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56412 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-21 21:11:41 +00:00
Owen Anderson
134eb73fc3
Fetch the starting index of the block when assigning intervals. This gets live-in indices
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correct in the presence of things like EH labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56410 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-21 20:43:24 +00:00
Chris Lattner
ca19a3fd11
don't print GlobalAddressSDNode's with an offset of zero as "foo0".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56399 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-21 18:38:31 +00:00
Dale Johannesen
34d8f7559c
Teach coalescer about earlyclobber bits.
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Check bits for preferred register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56384 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-20 02:03:04 +00:00
Evan Cheng
5e8d9def77
Fix PR2808. When regalloc runs out of register, it spill a physical register around the live interval being allocated. Do not continue to try to spill another register, just grab the physical register and move on.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56381 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-20 01:28:05 +00:00
Evan Cheng
fee2d6937c
Continue after removing the current MI.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56372 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-19 22:49:39 +00:00
Dan Gohman
2ff7fd1461
Refactor X86SelectConstAddr, folding it into X86SelectAddress. This
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results in better code for globals. Also, unbreak the local CSE for
GlobalValue stub loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56371 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-19 22:16:54 +00:00
Dale Johannesen
d6bd733534
Make earlyclobber stuff work when virtual regs
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have previously been assigned conflicting physreg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56364 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-19 18:52:31 +00:00
Evan Cheng
20580a1cf6
Re-materalized definition instructions may be dead. Whack them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56352 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-19 17:38:47 +00:00
Dale Johannesen
fa48f94130
Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysis
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and redo as linked list walk. Logic moved into RA.
Per review feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56326 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-19 01:02:35 +00:00
Evan Cheng
841ee1a12b
Somehow RegAllocLinearScan is keeping two pointers to MachineRegisterInfo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56314 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-18 22:38:47 +00:00
Dan Gohman
e251b1529f
Don't consider instructions with implicit physical register
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defs to be necessarily live.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56310 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-18 18:22:32 +00:00
Dan Gohman
ee2e403545
Add a new "fast" scheduler. This is currently basically just a
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copy of the BURRList scheduler, but with several parts ripped
out, such as backtracking, online topological sort maintenance
(needed by backtracking), the priority queue, and Sethi-Ullman
number computation and maintenance (needed by the priority
queue). As a result of all this, it generates somewhat lower
quality code, but that's its tradeoff for running about 30%
faster than list-burr in -fast mode in many cases.
This is somewhat experimental. Moving forward, major pieces of
this can be refactored with pieces in common with
ScheduleDAGRRList.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-18 16:26:26 +00:00
Dale Johannesen
91aac1015e
Add a bit to mark operands of asm's that conflict
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with an earlyclobber operand elsewhere. Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way
that conflicts with an earlyclobber. See also comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56290 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 21:13:11 +00:00
Evan Cheng
870e4bef41
Unallocatable registers do not have live intervals.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56287 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 18:36:25 +00:00
Dan Gohman
59932584a8
Don't worry about clobbering physical register defs that aren't used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56281 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 15:25:49 +00:00
Dan Gohman
d3ead4329e
Add a new MachineInstr-level DCE pass. It is very simple, and is intended to
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be used with fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56268 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 00:43:24 +00:00
Evan Cheng
1cd332725f
When converting a CopyFromReg to a copy instruction, use the register class of its uses to determine the right destination register class of the copy. This is important for targets where a physical register may belong to multiple register classes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56258 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 23:12:11 +00:00
Dan Gohman
50284d81f8
Change SelectionDAG::getConstantPool to always set the alignment of the
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ConstantPoolSDNode, using the target's preferred alignment for the
constant type.
In LegalizeDAG, when performing loads from the constant pool, the
ConstantPoolSDNode's alignment is used in the calls to getLoad and
getExtLoad.
This change prevents SelectionDAG::getLoad/getExtLoad from incorrectly
choosing the ABI alignment for constant pool loads when Alignment == 0.
The incorrect alignment is only a performance issue when ABI alignment
does not equal preferred alignment (i.e., on x86 it was generating
MOVUPS instead of MOVAPS for v4f32 constant loads when the default ABI
alignment for 128bit vectors is forced to 1 byte.)
Patch by Paul Redmond!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56253 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 22:05:41 +00:00
Bill Wendling
056292fd73
Reverting r56249. On further investigation, this functionality isn't needed.
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Apologies for the thrashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56251 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 21:48:12 +00:00
Dan Gohman
aed48bfee8
Include the alignment value when displaying ConstantPoolSDNodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56250 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 21:18:22 +00:00
Bill Wendling
9468a9b6be
- Change "ExternalSymbolSDNode" to "SymbolSDNode".
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- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol
These changes pave the way to allowing SymbolSDNodes with non-external linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56249 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 21:12:30 +00:00
Dan Gohman
05ae98346a
Fix these comments to reflect current reality. Surprisingly,
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MachineConstantPool::getConstantPoolIndex actually expects
a log2-encoded alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56248 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 20:45:53 +00:00
Dan Gohman
1937e2f6ca
Don't take the time to CheckDAGForTailCallsAndFixThem when tail calls
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are not enabled. Instead just omit the tail call flag when calls are
created.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56235 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 01:42:28 +00:00
Owen Anderson
99500aeb7c
Live intervals for live-in registers should begin at the beginning of a basic block, not at the first
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instruction. Also, their valno's should have an unknown def. This has no effect currently, but was
causing issues when StrongPHIElimination was enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56231 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-15 22:00:38 +00:00
Dan Gohman
5eb0cecbc5
Re-enable SelectionDAG CSE for calls. It matters in the case of
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libcalls, as in this testcase on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56226 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-15 19:46:03 +00:00