Evan Cheng
28dad2a5ca
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:31:17 +00:00
Jakob Stoklund Olesen
535af4a320
ARMBaseRegisterInfo::estimateRSStackSizeLimit() could return prematurely with a
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too large limit.
The function would return immediately when finding an addrmode 3/5 instruction.
It needs to keep scanning in case there is an addrmode 6 instruction which drops
the limit to 0.
A test case is very difficult to produce because it will only fail when the
scavenger is used.
rdar://problem/7894847
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103995 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 23:29:23 +00:00
Evan Cheng
47006be498
vmov of immediates are trivially re-materializable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103982 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 21:54:50 +00:00
Bob Wilson
7f43fd84db
Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests.
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Obvious in retrospect but not fun to debug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103969 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 20:31:13 +00:00
Evan Cheng
6206124250
Turn on -neon-reg-sequence by default.
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Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103960 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 19:51:20 +00:00
Evan Cheng
9c207ac0dc
No reason not to run the NEON domain croassing fix up pass in thumb2 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 01:11:46 +00:00
Anton Korobeynikov
bd91ea53f8
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-16 09:15:36 +00:00
Anton Korobeynikov
4878b8415f
Generalize the ARM DAG combiner of mul with constants to all power-of-two cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-16 08:54:20 +00:00
Evan Cheng
8f6de385d6
Model vst lane instructions with REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103898 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-16 03:27:48 +00:00
Anton Korobeynikov
a9790d739a
Some cheap DAG combine goodness for multiplication with a particular constant.
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This can be extended later on to handle more "complex" constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103881 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 18:16:59 +00:00
Anton Korobeynikov
418d1d954d
"trap" pseudo-op turned out to be apple-local.
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Temporary emit it as raw bytes until it will be added to binutils as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 17:19:20 +00:00
Evan Cheng
7189fd03fa
Model 128-bit vld lane with REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103868 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 07:53:37 +00:00
Evan Cheng
4782b1e2ca
v4i64 and v8i64 are only synthesizable when NEON is available.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103855 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 02:20:21 +00:00
Evan Cheng
06b666c705
Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
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allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 02:18:07 +00:00
Evan Cheng
7092c2bfcb
Model 64-bit lane vld with REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103851 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 01:36:29 +00:00
Evan Cheng
b990a2f249
Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
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instructions.
e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
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%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12
After REG_SEQUENCE is eliminated, we are left with:
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible,
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 23:21:14 +00:00
Evan Cheng
12c24690c7
Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103833 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 22:54:52 +00:00
Bill Wendling
b92187a410
Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what
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the variable actually tracks.
N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103802 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 21:14:32 +00:00
Evan Cheng
5c6aba2e3a
Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103790 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 18:54:59 +00:00
Evan Cheng
22c687b642
Added a QQQQ register file to model 4-consecutive Q registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 02:13:41 +00:00
Evan Cheng
7f68719517
Fix comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103749 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 00:21:45 +00:00
Evan Cheng
c4ca40eb5e
Add comment about the pseudo registers QQ, each of which is a pair of Q registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103731 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 20:02:08 +00:00
Bob Wilson
1190c14b54
Fix pr7110: For non-Darwin targets UnspilledCS1GPRs may include high registers.
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Do not use those for Thumb1 functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 19:58:24 +00:00
Daniel Dunbar
1860e7dcfd
Fix -Asserts warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103694 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 03:19:36 +00:00
Evan Cheng
69b9f9883e
Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103692 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 01:12:06 +00:00
Evan Cheng
d929f77738
Expand VMOVQQ into a pair of VMOVQ.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103684 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 00:17:02 +00:00
Evan Cheng
020cc1b4d0
Mark some pattern-less instructions as neverHasSideEffects.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103683 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 00:16:46 +00:00
Evan Cheng
431300797b
Fix some potential issues in the pseudo instruction expansion phase: copy implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 23:13:12 +00:00
Evan Cheng
a4d73d01c4
Remove a dead fixme.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 20:20:22 +00:00
Rafael Espindola
18c1021ec1
Add support for movi32 of global values to the new (MC) asm printer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103576 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 05:16:34 +00:00
Evan Cheng
5bdc2aa264
vst instructions are modeled as this:
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v1024 = REG_SEQUENCE ...
v1025 = EXTRACT_SUBREG v1024, 5
v1026 = EXTRACR_SUBREG v1024, 6
= VSTxx <addr>, v1025, v1026
The REG_SEQUENCE ensures the sources that feed into the VST instruction
are getting the right register allocation so they form a large super-
register. The extract_subreg will be coalesced away all would just work:
v1024 = REG_SEQUENCE ...
= VSTxx <addr>, v1024:5, v1024:6
The problem is if the coalescer isn't run, the extract_subreg instructions
would stick around and there is no assurance v1025 and v1026 will get the
right registers.
As a short term workaround, teach the NEON pre-allocation pass to transfer
the sub-register indices over. An alternative would be do it 2addr pass
when reg_sequence's are eliminated. But that *seems* wrong and require
updating liveness information.
Another alternative is to do this in the scheduler when the instructions are
created. But that would mean somehow the scheduler this has to be done for
correctness reason. That's yucky as well. So for now, we are leaving this
in the target specific pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103540 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 01:42:50 +00:00
Evan Cheng
9647f3d981
Avoid breaking vstd when reg_sequence is not used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 21:07:36 +00:00
Duncan Sands
16d8f8bd91
I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it
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to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103495 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 20:16:09 +00:00
Dan Gohman
ff7a562751
Implement a bunch more TargetSelectionDAGInfo infrastructure.
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Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 17:31:57 +00:00
Dan Gohman
419e4f9263
Remove the TargetLowering::getSubtarget() virtual function, which
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was unused. TargetMachine::getSubtarget() is used instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103474 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 16:21:03 +00:00
Evan Cheng
fb3611daad
Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103459 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 07:26:32 +00:00
Evan Cheng
0ce537a9db
Model some vst3 and vst4 with reg_sequence.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 01:19:40 +00:00
Evan Cheng
e9e2ba05de
Model some vld3 instructions with REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103437 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-10 21:26:24 +00:00
Evan Cheng
603afbfe2a
Model vld2 / vst2 with reg_sequence.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103411 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-10 17:34:18 +00:00
Jim Grosbach
4b77f6a85a
Clean up the conditional for handling of sign_extend_inreg based on
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whether the extract instructions are available.
rdar://7956878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103277 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 18:34:55 +00:00
Evan Cheng
435d499177
Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103235 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 02:04:02 +00:00
Evan Cheng
07a6d9391c
Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103234 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 01:54:08 +00:00
Evan Cheng
c10b5afbe8
Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103218 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 00:24:52 +00:00
Dan Gohman
34dcc6fadc
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
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doesn't have to guess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:33:48 +00:00
Evan Cheng
746ad69e08
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 19:06:44 +00:00
Bob Wilson
429009b0f1
Add a missing break statement to fix unintentional fall-through
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(replacing the previous patch for the same issue).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 16:05:26 +00:00
Jim Grosbach
d31f00b7f7
Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com>
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103181 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 15:32:49 +00:00
Shantonu Sen
eae216c6d3
Fix "warning: extra ';' inside a struct or union" when building llvm with clang
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103179 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 14:57:47 +00:00
Evan Cheng
b63387afc6
Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 06:36:08 +00:00
Dan Gohman
1ef7c82128
Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103163 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 05:08:57 +00:00