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89f4e6639d
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21504 Commits

Author SHA1 Message Date
Craig Topper
89f4e6639d Remove code that prevented lowering shuffles if they are used by load and themselves used by a extract_vector_elt. This was done to allow the DAG combiner to collapse to a single element load. Unfortunately, sometimes the extract_vector_elt would disappear before DAG combine could do the transformation leaving a vector_shuffle that isel couldn't handle. New code lets the shuffle be converted to a target specific node, but then adds a combine routine that can convert target specific nodes back to vector_shuffles if the folding criteria are met. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153080 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 07:17:59 +00:00
Craig Topper
a1ffc681ed Factor out target shuffle mask decoding from getShuffleScalarElt and use a SmallVector of int instead of unsigned for shuffle mask in decode functions. Preparation for another change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153079 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 06:42:26 +00:00
Chris Lattner
e59b0e777d fix a build failure with libc++ 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153063 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 23:31:01 +00:00
Jim Grosbach
fa1f74470a ARM branch relaxation for unconditional t1 branches. 
rdar://11059157

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153055 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 21:32:32 +00:00
Jim Grosbach
ceee984302 ARM assembly, accept optional '#' on lane index number. 
rdar://11057160

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153053 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 20:39:53 +00:00
Anton Korobeynikov
2d7ea04e28 Perform mul combine when multiplying wiht negative constants. 
Patch by Weiming Zhao!
This fixes PR12212


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153049 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 19:19:50 +00:00
Preston Gurd
3e99b715d1 This patch adds X86 instruction itineraries for non-pseudo opcodes in 
X86InstrCompiler.td.
 
It also adds –mcpu-generic to the legalize-shift-64.ll test so the test
will pass if run on an Intel Atom CPU, which would otherwise
produce an instruction schedule which differs from that which the test expects.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153033 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 14:10:12 +00:00
Benjamin Kramer
8118c94a55 Add a note for -ffast-math optimization of vector norm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153031 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 00:43:34 +00:00
Craig Topper
97327dc6ef isCommutedMOVLMask should only look at 128-bit vectors to match isMOVLMask. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153027 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-18 22:50:10 +00:00
Craig Topper
79aa3417eb Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-17 18:46:09 +00:00
Craig Topper
70de1e442d Fix some copy and paste remnants of Cell and SPU in Hexagon files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152981 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-17 09:39:20 +00:00
Craig Topper
8aea2dd964 Fix typo in file header. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152980 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-17 09:28:37 +00:00
Craig Topper
1e0c9ab0d1 Pass TargetOptions to HexagonTargetMachine constructor by reference to match other targets and the base class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152979 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-17 09:24:09 +00:00
Craig Topper
c1f6f42049 Reorder includes to match coding standards. Fix an issue or two exposed by that. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152978 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-17 07:33:42 +00:00
Bill Wendling
5aeff3171c Check if we can handle the arguments of a call (and therefore the call) in 
fast-isel before emitting code. If the program bails after code was emitted,
then it could lead to the stack being adjusted more than once (two
CALLSEQ_BEGINs emitted) but being adjuste back only once after the call. This
leads to general badness and gnashing of teeth.
<rdar://problem/11050630>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152959 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 23:11:07 +00:00
Jim Grosbach
11d5dc3d50 ARM fix silly typo in optional operand alias. 
rdar://11065671

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152954 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 22:18:29 +00:00
Jim Grosbach
66cba302f0 ARM divided syntax fmrx/fmxr mnemonics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152946 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 21:06:13 +00:00
Jim Grosbach
be7cf2b377 ARM ldm/stm register lists can be out of order. 
It's not a good style idea, as the registers will be laid down in memory in
numerical order, not the order they're in the list, but it's legal. vldm/vstm
are stricter.

rdar://11064740

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152943 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 20:48:38 +00:00
Jim Grosbach
213d2e7dc3 ARM optional operand on MRC/MCR assembly instructions. 
rdar://11058464

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152883 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 00:45:58 +00:00
Jim Grosbach
9426ac7b57 ARM vmrs system registers mvfr0 and mvfr1 handling. 
rdar://11058464

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152881 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 00:27:18 +00:00
Jim Grosbach
89eaa6f554 Remove inadvertant commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152870 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 23:00:30 +00:00
Chad Rosier
0ac754f6f4 [fast-isel] Address Eli's comments for r152847. Specifically, add a test case 
and still allow immediate encoding, just not with cmn.
rdar://11038907


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152869 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 22:54:20 +00:00
Chad Rosier
530b19b702 [fast-isel] Don't try to encode LONG_MIN using cmn instructions. 
rdar://11038907


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152847 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 21:40:23 +00:00
Jim Grosbach
b84ad4aa7d ARM case-insensitive checking for APSR_nzcv. 
rdar://11056591

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152846 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 21:34:14 +00:00
Jim Grosbach
6357caec78 ARM aliases for pre-unified syntax fcmpz[sd] mnemonics. 
rdar://11056647

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152834 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 20:48:18 +00:00
Lang Hames
45b5f88938 Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints on 
register allocation by allowing all 32 D-registers to be used. Patch by Cameron
Zwarich.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152824 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 18:49:02 +00:00
Kristof Beyls
8a6bcc3722 Fix VCVT decoding (between floating-point and fixed-point, Floating-point). Patch by Richard Barton. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152814 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 17:50:29 +00:00
Chad Rosier
38ca0d78a2 [avx] Add patterns for VINSERTF128rm. 
This results in things such as

	vmovaps	-96(%rbx), %xmm1
	vinsertf128	$1, %xmm1, %ymm0, %ymm0

to be combined to
         
	vinsertf128	$1, -96(%rbx), %ymm0, %ymm0

rdar://10643481

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152762 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 00:45:30 +00:00
Kevin Enderby
0f5ab7c5f3 Change the X86 assembler to not require a segment register on string 
instruction's destination operand like it does for the source operand.
Also fix a typo in the comment for X86AsmParser::isSrcOp().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152654 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-13 19:47:55 +00:00
Kevin Enderby
84faf65912 Added a missing error check for X86 assembly with mismatched base and index 
registers not both being 64-bit or both being 32-bit registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152580 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-12 21:32:09 +00:00
Bob Wilson
2bbb22b8ef Switch to unified syntax for VFP instructions in inline assembly. 
<rdar://problem/11024696>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152548 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-12 06:15:36 +00:00
Benjamin Kramer
57a76605f0 Remove global map. This code isn't even hot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152544 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-11 18:12:04 +00:00
Craig Topper
c5eaae4e9b Convert more static tables of registers used by calling convention to uint16_t to reduce space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-11 07:57:25 +00:00
Craig Topper
b78ca42384 Use uint16_t to store registers and opcode in static tables in the target specific backends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152537 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-11 07:16:55 +00:00
Craig Topper
048e9bdbeb Remove unused functions getArgRegs and getNumArgRegs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152535 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-11 06:46:40 +00:00
Stepan Dyatkovskiy
3d3abe0852 llvm::SwitchInst 
Renamed methods caseBegin, caseEnd and caseDefault with case_begin, case_end, and case_default.
Added some notes relative to case iterators.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152532 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-11 06:09:17 +00:00
Kay Tiong Khoo
5a08cf4d34 *fix typo in comment; test of commit access 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152507 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-10 21:29:49 +00:00
Benjamin Kramer
63155f967c C files in llvm still have to be C89 compliant, remove C++-style comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152495 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-10 15:10:06 +00:00
Bill Wendling
e060eb8916 Fix disasm of iret, sysexit, and sysret when displayed with Intel syntax. 
Patch by Kay Tiong Khoo!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152487 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-10 07:37:27 +00:00
Akira Hatanaka
d229b7b8f4 Do not custom lower i64 nodes if i64 is not a legal type. Move lines that set 
operation action of nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152452 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-10 00:03:50 +00:00
Akira Hatanaka
0a40c2353c Lower SETCC nodes during legalization. Previously, it was lowered in DAG combine pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152450 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-09 23:46:03 +00:00
Akira Hatanaka
6e1beea6bf Remove unused header files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152447 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-09 23:28:30 +00:00
Kevin Enderby
58dfaa1465 Add the missing call to Error when a bad X86 scale expression is parsed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152443 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-09 22:24:10 +00:00
Kevin Enderby
faf72ffda3 Fix the x86 disassembler to at least print the lock prefix if it is the first 
prefix.  Added a FIXME to remind us this still does not work when it is not the
first prefix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152414 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-09 17:52:49 +00:00
Craig Topper
72051bf629 Use uint16_t to store opcodes in static tables in X86 backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152391 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-09 07:45:21 +00:00
Ahmed Charles
e38ec24758 Fix undefined behavior in the Mips backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152390 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-09 06:36:45 +00:00
Chad Rosier
abd6674166 Fix a regression from r147481. 
Original commit message from r147481:
DAGCombine for transforming 128->256 casts into a vmovaps, rather
then a vxorps + vinsertf128 pair if the original vector came from a load.

Fix:
Unaligned loads need to generate a vmovups.
rdar://10974078



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152366 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-09 02:00:48 +00:00
Craig Topper
fac2598149 Use uint16_t to store instruction implicit uses and defs. Reduces static data. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152301 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-08 08:22:45 +00:00
Stepan Dyatkovskiy
c10fa6c801 Taken into account Duncan's comments for r149481 dated by 2nd Feb 2012: 
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20120130/136146.html

Implemented CaseIterator and it solves almost all described issues: we don't need to mix operand/case/successor indexing anymore. Base iterator class is implemented as a template since it may be initialized either from "const SwitchInst*" or from "SwitchInst*".

ConstCaseIt is just a read-only iterator.
CaseIt is read-write iterator; it allows to change case successor and case value.

Usage of iterator allows totally remove resolveXXXX methods. All indexing convertions done automatically inside the iterator's getters.

Main way of iterator usage looks like this:
SwitchInst *SI = ... // intialize it somehow

for (SwitchInst::CaseIt i = SI->caseBegin(), e = SI->caseEnd(); i != e; ++i) {
  BasicBlock *BB = i.getCaseSuccessor();
  ConstantInt *V = i.getCaseValue();
  // Do something.
}

If you want to convert case number to TerminatorInst successor index, just use getSuccessorIndex iterator's method.
If you want initialize iterator from TerminatorInst successor index, use CaseIt::fromSuccessorIndex(...) method.

There are also related changes in llvm-clients: klee and clang.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152297 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-08 07:06:20 +00:00
Akira Hatanaka
ee8c3b03fb Invoke setTargetDAGCombine for SELECT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152290 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-08 03:26:37 +00:00