Commit Graph

5692 Commits

Author SHA1 Message Date
Jim Grosbach
8a12e3b5df ARM allows '' syntax, not just '#imm' for assembly.
Backwards compatibility with 'gas'. #imm is the preferered and documented
syntax, but lots of existing code uses the '$' prefix, so we should
support it if we can.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146285 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 22:25:03 +00:00
Jim Grosbach
840bf7eda7 ARM assembly aliases for BIC<-->AND (immediate).
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.

rdar://10550057


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 22:02:17 +00:00
Jim Grosbach
4332983e77 ARM NEON data type aliases for VBIC(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146281 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 21:46:04 +00:00
Jim Grosbach
a4e3c7fc4b ARM assembly parsing and encoding for VLD2 with writeback.
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 21:28:25 +00:00
Jakob Stoklund Olesen
493ad6b95d User a helper overload for a common pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146270 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 19:44:39 +00:00
Jim Grosbach
2af50d981d Tidy up. Better base class factoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146267 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 19:07:20 +00:00
Jim Grosbach
1f94ec7b59 Tidy up. Better base class factoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146266 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 18:54:11 +00:00
Jakob Stoklund Olesen
3c4615eef2 Tweak debugging output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146264 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 18:20:35 +00:00
Jim Grosbach
976c0da213 ARM convenience aliases for VSQRT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146201 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:51:25 +00:00
Jim Grosbach
8759c3f548 ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146194 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:19:04 +00:00
Jim Grosbach
6b044c2609 ARM VSHR implied destination operand form aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:06:06 +00:00
Jim Grosbach
a62d11ea94 ARM asm parser, just issue a warning for a duplicate reg in a list.
For better 'gas' compatibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146185 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 21:34:20 +00:00
Jim Grosbach
120313435d ARM VSUB implied destination operand form aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146182 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:56:26 +00:00
Jim Grosbach
9e7b42a40e ARM VQADD implied destination operand form aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:49:43 +00:00
Jim Grosbach
1c2c8a9389 ARM a few more VMUL implied destination operand form aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146177 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:42:35 +00:00
Jim Grosbach
40e2855547 ARM assembler support for register name aliases.
rdar://10550084

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 19:27:38 +00:00
Daniel Dunbar
3b0887e291 Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146157 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 17:32:18 +00:00
Stepan Dyatkovskiy
72590c9738 Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146143 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 07:55:03 +00:00
Jim Grosbach
730fe6c1b6 ARM NEON two-operand aliases for VSHL(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:30:04 +00:00
Jakob Stoklund Olesen
e6f9e9d836 Drop the HasInlineAsm flag.
It is not used any more. We are tracking inline assembly misalignments
directly through the BBInfo.Unalign and KnownBits fields.

A simple conservative size estimate is not good enough since it can
cause alignment padding to be underestimated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146124 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:22:39 +00:00
Jim Grosbach
ff4cbb4c9a ARM NEON two-operand aliases for VSHL(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146123 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:12:35 +00:00
Jakob Stoklund Olesen
99486be8ba Simplify offset verification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146121 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:10:05 +00:00
Jim Grosbach
517a013a4f Fix copy/past-o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146120 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:02:26 +00:00
Jim Grosbach
2b8810c500 ARM NEON two-operand aliases for VMUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146119 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:59:47 +00:00
Jakob Stoklund Olesen
540c6d9d26 Don't include alignment padding in BBInfo.Size.
Compute alignment padding before and after basic blocks dynamically.

Heed basic block alignment.

This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size.  It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.

This makes the ARMConstantIslandPass aware of aligned basic blocks.

It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size.  If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected.  This could cause constant
pool entries to move out of range.

To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly.  Normal
functions should be unaffected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146118 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:55:02 +00:00
Jim Grosbach
8254f02231 ARM VFP support 'fmrs/fmsr' aliases for 'vldr'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146116 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:52:55 +00:00
Jim Grosbach
67ca1adf82 ARM VFP support 'flds/fldd' aliases for 'vldr'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146115 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:49:29 +00:00
Jim Grosbach
a44f2c4a28 ARM optional destination operand variants for VEXT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146114 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:43:47 +00:00
Jim Grosbach
3bc8a3d3af ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:31:07 +00:00
Jim Grosbach
af4edea67b ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
For 'gas' compatibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:40:58 +00:00
Jim Grosbach
9fa0a743e6 ARM two-operand aliases for VAND/VEOR/VORR instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:08:12 +00:00
Jim Grosbach
30a264eb7f ARM two-operand aliases for VADDW instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146093 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:01:10 +00:00
Jim Grosbach
d900441e13 ARM two-operand aliases for VADD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146091 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 22:52:54 +00:00
Jim Grosbach
4f66a050a2 Nuke inadvertant debugging commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 19:56:16 +00:00
Jim Grosbach
577b09155f Darwin assembler improved relocs when w/o subsections_via_symbols.
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146054 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 19:46:59 +00:00
Jim Grosbach
8524bca750 Thumb2 alias for long-form pop and friends.
rdar://10542474

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 18:32:28 +00:00
Jim Grosbach
9a70df99ca ARM support the .arm and .thumb directives for assembly mode switching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 18:04:19 +00:00
Jim Grosbach
470855b24f ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146039 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 17:51:15 +00:00
Evan Cheng
5a96b3dad2 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 07:15:52 +00:00
Jakob Stoklund Olesen
2fe71c5ef4 Eliminate delta argument from AdjustBBOffsetsAfter.
The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.

Eliminate one redundant AdjustBBOffsetsAfter call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146018 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 05:17:30 +00:00
Jakob Stoklund Olesen
a26811ec83 Compute some alignment information for each basic block.
These fields are not used for anything yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 04:17:35 +00:00
Jim Grosbach
1ceef1a491 ARM tidy up and remove no longer needed InstAlias definitions.
The TokenAlias handling of data type suffices renders these unnecessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146010 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:50:36 +00:00
Jakob Stoklund Olesen
5bb32530bc Move common expression into a method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146008 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:22:52 +00:00
Jim Grosbach
9f3d220c63 ARM Implement ARM ARM Table A7-3 via TokenAlias.
Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.

rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146007 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:17:58 +00:00
Jakob Stoklund Olesen
a3f331bd81 Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>.
No functional change is intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:08:25 +00:00
Jim Grosbach
3b8991cc98 ARM: NEON SHLL instruction immediate operand range checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:07:24 +00:00
Jim Grosbach
4e4139588c ARM: Parameterize the immediate operand type for NEON VSHLL.
No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145994 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 00:02:17 +00:00
Jakob Stoklund Olesen
6fbea43b0b Revert r145971: "Use conservative size estimate for tBR_JTr."
This caused more offset errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145980 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 22:41:31 +00:00
Evan Cheng
7c2a4a30e0 First chunk of MachineInstr bundle support.
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 22:12:01 +00:00
Jakob Stoklund Olesen
d25c27807e Use conservative size estimate for tBR_JTr.
This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.

It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145971 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 21:55:39 +00:00