6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-28 21:34:23 +00:00
Code Issues Projects Releases Wiki Activity
53,947 Commits 39 Branches 0 Tags
Commit Graph

12880 Commits

Author SHA1 Message Date
Jim Grosbach
8a5ec86a3d Support alignment specifier for NEON vld/vst instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86404 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 21:25:39 +00:00
Nick Lewycky
f80fcd00b3 Improve tail call elimination to handle the switch statement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86403 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 21:10:15 +00:00
Evan Cheng
bf992817f2 t2ldrpci_pic can be used for blockaddress as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86400 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 19:40:04 +00:00
Chris Lattner
59a9178fbe indicate what the native integer types for the target are. 
Please verify.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86397 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 19:07:32 +00:00
Anton Korobeynikov
06ac0820a6 First try of the post-inc operands handling... Not fully worked, though :( 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86386 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 17:15:25 +00:00
Anton Korobeynikov
6534f83ae8 Add some dummy support for post-incremented loads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86385 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 17:15:06 +00:00
Anton Korobeynikov
8983da729a Add 8 bit libcalls and make use of them for msp430 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86384 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 17:14:39 +00:00
Anton Korobeynikov
8046ef4379 Add few pseudo-source-values 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86383 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 17:13:57 +00:00
Anton Korobeynikov
123ed8f099 Initial support for addrmode handling. Tests by Brian Lucas! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86382 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 17:13:35 +00:00
Anton Korobeynikov
603fce9ebb Some preliminary variable asmprinting 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86381 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 17:12:58 +00:00
Anton Korobeynikov
5c192fbe45 Use '.L' for global private prefix (as mspgcc) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86380 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 17:12:38 +00:00
Anton Korobeynikov
b7790e11c4 Drop old asmprinter stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86379 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 17:12:21 +00:00
Anton Korobeynikov
e8ea011cc7 It turns out that the testcase in question uncovered subreg-handling bug. 
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86375 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 15:20:32 +00:00
Chris Lattner
e82bdc4809 add the ability for TargetData to return information about legal integer 
datatypes on a given CPU.  This is intended to allow instcombine and other
transformations to avoid converting big sequences of operations to an
inconvenient width, and will help clean up after SRoA.  See also "Adding 
legal integer sizes to TargetData" on Feb 1, 2009 on llvmdev, and PR3451.

Comments welcome.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86370 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 09:35:34 +00:00
Chris Lattner
2e07494170 more cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86369 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 09:23:04 +00:00
Chris Lattner
8f9b0f6e88 add some missing #includes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86367 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 09:20:54 +00:00
Chris Lattner
b7aadfac5e rewrite TargetData to use StringRef/raw_ostream instead of thrashing std::strings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86366 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 09:13:23 +00:00
Jeffrey Yasskin
2d274412ed Make the need-stub variables accurate and consistent. In the case of 
MachineRelocations, "stub" always refers to a far-call stub or a
load-a-faraway-global stub, so this patch adds "Far" to the term. (Other stubs
are used for lazy compilation and dlsym address replacement.) The variable was
also inconsistent between the positive and negative sense, and the positive
sense ("NeedStub") was more demanding than is accurate (since a nearby-enough
function can be called directly even if the platform often requires a stub).
Since the negative sense causes double-negatives, I switched to
"MayNeedFarStub" globally.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86363 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 08:51:52 +00:00
Eric Christopher
761411c21b Fix a couple of shuffle patterns to use movhlps instead 
of movhps as the constraint.  Changes optimizations so
update testcases as appropriate as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86360 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 08:45:53 +00:00
Mon P Wang
0ace1a9f30 Fixed Overload table bug noticed by Jakob 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86332 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 04:07:33 +00:00
Evan Cheng
d457e6e9a5 Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86330 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 04:04:34 +00:00
Evan Cheng
78e5c1140a - Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical 
except it doesn't care if the definitions' virtual registers differ. This is
  used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
  Since pc relative constantpool entries are always different, this requires it
  it check if the values can actually the same.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86328 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 03:52:02 +00:00
Ted Kremenek
b6aae88ac0 Update CMake file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86325 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 03:26:59 +00:00
Kenneth Uildriks
b4997aeab7 Add code to check at SelectionDAGISel::LowerArguments time to see if return values can be lowered to registers. Coming soon, code to perform sret-demotion if return values cannot be lowered to registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86324 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 02:11:54 +00:00
Johnny Chen
0430152a11 My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm 
was wrong and too aggressive in the sense that DPSoRegFrm includes both constant
shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and
Inst{7} = 0).  The 'rr' fragment of the multiclass definitions actually means
register/register with no shift, see A8-11.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86319 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 00:54:36 +00:00
Jim Grosbach
bd79fc8ef2 80-columns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86310 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 00:13:30 +00:00
Evan Cheng
b9803a8fa6 - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative 
load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86304 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 23:52:48 +00:00
Anton Korobeynikov
fc2cba8362 Honour subreg machine operands during asmprinting 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86303 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 23:45:15 +00:00
Bob Wilson
54c78ef2fe Print VMOV (immediate) operands as hexadecimal values. Apple's assembler 
will not accept negative values for these.  LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates.  Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86301 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 23:33:28 +00:00
Evan Cheng
e7e0d62efd Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86294 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 22:24:13 +00:00
Daniel Dunbar
2928c83b01 Pass StringRef by value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86251 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 10:58:06 +00:00
Dan Gohman
40c57860da Factor out the printing of the leading tab into printInlineAsm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86199 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 00:04:54 +00:00
Dan Gohman
7289ed2ee7 Use SUBREG_TO_REG instead of INSERT_SUBREG to model x86-64's 
implicit zero-extend.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86196 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-05 23:53:08 +00:00
Dan Gohman
73bb251cd7 Remove uninteresting and confusing debug output. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86149 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-05 18:47:09 +00:00
Chris Lattner
6c9fab7404 add a note from PR5313 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86146 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-05 18:19:19 +00:00
Mon P Wang
82c443655d Reintroduce support for overloading target intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86114 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-05 03:19:08 +00:00
Jim Grosbach
4371cda7f8 Grammar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86068 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 23:20:40 +00:00
Jim Grosbach
db1751a922 Now that the memory leak from McCat/08-main has been fixed (86056), re-enable 
aggressive testing of dynamic stack alignment.
Note that this is off by default, and enabled for LLCBETA nightly results.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86064 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 23:11:07 +00:00
Jim Grosbach
6db06a0866 If a function has no stack frame at all, dynamic realignment isn't necessary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86057 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 22:41:51 +00:00
Jim Grosbach
c5848f4ced dynamic stack realignment necessitates scanning the floating point callee- 
saved instructions even if no stack adjustment for those saves is needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86056 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 22:41:00 +00:00
Bob Wilson
3d90dbee69 Add PowerPC codegen for indirect branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86050 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 21:31:18 +00:00
Jakob Stoklund Olesen
ad68264f59 Print out an informative comment for KILL instructions. 
The KILL pseudo-instruction may survive to the asm printer pass, just like the IMPLICIT_DEF. Print the KILL as a comment instead of just leaving a blank line in the output.

With -asm-verbose=0, a blank line is printed, like IMPLICIT?DEF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86041 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 19:24:37 +00:00
Evan Cheng
b9f51cbe98 The .n suffix must go after the predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86019 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 07:38:48 +00:00
Evan Cheng
7883fa942f Use ldr.n to workaround a darwin assembler bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85980 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 00:00:39 +00:00
Evan Cheng
5a1cd36019 Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85965 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 23:13:34 +00:00
Evan Cheng
b23b2015eb fconsts / fconstd immediate should be proceeded with #. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85952 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 21:59:33 +00:00
Anton Korobeynikov
747409a290 Move subtarget check upper for NEON reg-reg fixup pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85914 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 18:46:11 +00:00
Evan Cheng
f6c0bffa8d Trim unnecessary include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85878 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 07:08:08 +00:00
Bob Wilson
af14e663ac For Thumb indirect branches, use "mov pc, reg" which does not switch 
between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85874 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 06:29:56 +00:00
Evan Cheng
ba908640b3 Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85871 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 05:52:54 +00:00