Commit Graph

108277 Commits

Author SHA1 Message Date
Matt Arsenault
8a70e28114 R600/SI: Don't move operands that are required to be SGPRs
e.g. v_cndmask_b32 requires the condition operand be an SGPR.
If one of the source operands were an SGPR, that would be considered
the one SGPR use and the condition operand would be illegally moved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218529 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 17:54:52 +00:00
Matt Arsenault
5b199b585c R600/SI: Don't assert on exotic operand types
This needs a test, but I'm not sure if it is currently possible and
I originally hit it due to a bug. Right now the only global address
operands have no reason to be VALU instructions, although it
theoretically could be a problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218528 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 17:54:46 +00:00
Matt Arsenault
26b2a7834e R600/SI: Fix using wrong operand indices when commuting
No test since the current SIISelLowering::legalizeOperands
effectively hides this, and the general uses seem to only fire
on SALU instructions which don't have modifiers between
the operands.

When trying to use legalizeOperands immediately after
instruction selection, it now sees a lot more patterns
it did not see before which break on this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218527 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 17:54:43 +00:00
Matt Arsenault
ea849e9adc R600/SI: Remove apparently dead code in legalizeOperands
No tests hit this, and I don't see any way a GlobalAddress
node would survive beyond lowering on SI. It it would, the
move should probably be inserted by selection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218526 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 17:54:38 +00:00
David Peixotto
ea468dddfe Ignore annotation function calls in cost computation
The annotation instructions are dropped during codegen and have no
impact on size.  In some cases, the annotations were preventing the
unroller from unrolling a loop because the annotation calls were
pushing the cost over the unrolling threshold.

Differential Revision: http://reviews.llvm.org/D5335



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218525 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 17:48:40 +00:00
Chandler Carruth
a7579ed23f [x86] The mnemonic is SHUFPS not SHUPFS. =[ I'm very bad at spelling
sadly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218524 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 17:27:40 +00:00
Chandler Carruth
7929a210d5 [x86] In the new vector shuffle lowering, when trying to do another
layer of tie-breaking sorting, it really helps to check that you're in
a tie first. =] Otherwise the whole thing cycles infinitely. Test case
added, another one found through fuzz testing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218523 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 17:24:26 +00:00
Chandler Carruth
7164a4ae0a [x86] Fix a large collection of bugs that crept in as I fleshed out the
AVX support.

New test cases included. Note that none of the existing test cases
covered these buggy code paths. =/ Also, it is clear from this that
SHUFPS and SHUFPD are the most bug prone shuffle instructions in x86. =[

These were all detected by fuzz-testing. (I <3 fuzz testing.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218522 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 17:11:02 +00:00
Renato Golin
6215f78195 Elide repeated register operand in Thumb1 instructions
This patch makes the ARM backend transform 3 operand instructions such as
'adds/subs' to the 2 operand version of the same instruction if the first
two register operands are the same.

Example: 'adds r0, r0, #1' will is transformed to 'adds r0, #1'.

Currently for some instructions such as 'adds' if you try to assemble
'adds r0, r0, #8' for thumb v6m the assembler would throw an error message
because the immediate cannot be encoded using 3 bits.

The backend should be smart enough to transform the instruction to
'adds r0, #8', which allows for larger immediate constants.

Patch by Ranjeet Singh.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218521 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 16:14:29 +00:00
Andrea Di Biagio
a5ab9baf83 [X86][SchedModel] SSE reciprocal square root instruction latencies.
The SSE rsqrt instruction (a fast reciprocal square root estimate) was
grouped in the same scheduling IIC_SSE_SQRT* class as the accurate (but very
slow) SSE sqrt instruction. For code which uses rsqrt (possibly with
newton-raphson iterations) this poor scheduling was affecting performances.

This patch splits off the rsqrt instruction from the sqrt instruction scheduling
classes and creates new IIC_SSE_RSQER* classes with latency values based on
Agner's table.

Differential Revision: http://reviews.llvm.org/D5370

Patch by Simon Pilgrim.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218517 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 12:56:44 +00:00
Frederic Riss
a0d5d7aed8 Revert "Store TypeUnits in a SmallVector<DWARFUnitSection> instead of a single DWARFUnitSection."
This reverts commit r218513.

Buildbots using libstdc++ issue an error when trying to copy
SmallVector<std::unique_ptr<>>. Revert the commit until we have a fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218514 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 12:34:06 +00:00
Frederic Riss
5fb5bdbf6a Store TypeUnits in a SmallVector<DWARFUnitSection> instead of a single DWARFUnitSection.
Summary:
There will be multiple TypeUnits in an unlinked object that will be extracted
from different sections. Now that we have DWARFUnitSection that is supposed
to represent an input section, we need a DWARFUnitSection<TypeUnit> per
input .debug_types section.

Once this is done, the interface is homogenous and we can move the Section
parsing code into DWARFUnitSection.

Reviewers: samsonov, dblaikie

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5482

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218513 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 12:15:40 +00:00
Daniel Sanders
12aa552637 Fix unused variable warning added in r218509
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218510 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 10:45:26 +00:00
Daniel Sanders
7ecd98679e [mips] Generalize the handling of f128 return values to support f128 arguments.
Summary:
This will allow us to handle f128 arguments without duplicating code from
CCState::AnalyzeFormalArguments() or CCState::AnalyzeCallOperands().

No functional change.

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5292

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218509 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 10:06:12 +00:00
Robert Khasanov
26ba182fdf [AVX512] Added load/store from BW/VL subsets to Register2Memory opcode tables.
Added lowering tests for these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218508 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 09:48:50 +00:00
David Majnemer
537364502a llvm-vtabledump: Small cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218505 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 08:01:23 +00:00
Jyoti Allur
72db9e5b09 fix a typo in doumentation index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218504 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 06:59:15 +00:00
David Majnemer
178cb752c7 llvm-vtabledump: strip trailing NUL bytes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218502 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 05:50:45 +00:00
David Majnemer
ed2b7578b8 Fix build breakage on MSVC 2013
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218499 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 04:47:54 +00:00
David Majnemer
035e22bc06 llvm-vtabledump: Dump RTTI structures for the MS ABI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218498 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 04:21:51 +00:00
David Majnemer
af100b0350 Target: Fix build breakage.
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218497 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 02:57:05 +00:00
David Majnemer
346056ffc0 Support: Remove undefined behavior from &raw_ostream::operator<<
Don't negate signed integer types in &raw_ostream::operator<<(const
FormattedNumber &FN).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218496 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 02:48:14 +00:00
David Xu
abf5bf221f Revert patch of r218493, delete the test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218495 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 02:40:54 +00:00
David Xu
2109982c88 Revert patch ofr218493
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218494 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 02:28:03 +00:00
David Xu
c41ae2a5c4 Redundant store instructions should be removed as dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218493 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 02:02:09 +00:00
Eric Christopher
55a90ab4ef Add the first backend support for on demand subtarget creation
based on the Function. This is currently used to implement
mips16 support in the mips backend via the existing module
pass resetting the subtarget.

Things to note:

a) This involved running resetTargetOptions before creating a
new subtarget so that code generation options like soft-float
could be recognized when creating the new subtarget. This is
to deal with initialization code in isel lowering that only
paid attention to the initial value.

b) Many of the existing testcases weren't using the soft-float
feature correctly. I've corrected these based on the check
values assuming that was the desired behavior.

c) The mips port now pays attention to the target-cpu and
target-features strings when generating code for a particular
function. I've removed these from one function where the
requested cpu and features didn't match the check lines in
the testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218492 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 01:44:08 +00:00
Eric Christopher
792f334305 Add a FIXME to TargetMachine to remove the function specific
code generation options from TargetMachine. This will depend
upon Function + TargetSubtargetInfo based code generation at
which point resetTargetOptions and this code can be removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218491 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 01:44:05 +00:00
Eric Christopher
eea543fd16 Have setSubtarget take a const subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218490 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 01:28:13 +00:00
Eric Christopher
a6e0a6e729 Move resetTargetOptions from taking a MachineFunction to a Function
since we are accessing the TargetMachine that we're a member
function of.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218489 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 01:28:10 +00:00
Matt Arsenault
deaa9d8c72 R600: Avoid repeated check lines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218487 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 01:12:36 +00:00
Matt Arsenault
584886c0bb R600/SI: Fix emitting trailing whitespace after s_waitcnt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218486 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 01:09:46 +00:00
Adam Nemet
479f2f7a14 [AVX512] Simplify use of !con()
No change in X86.td.expanded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218485 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 00:53:12 +00:00
Adam Nemet
08f261afbf [AVX512] Pull pattern for subvector extract into the instruction definition
No functional change.

I initially thought that pulling the Pat<> into the instruction pattern was
not possible because it was doing a transform on the index in order to convert
it from a per-element (extract_subvector) index into a per-chunk (vextract*x4)
index.

Turns out this also works inside the pattern because the vextract_extract
PatFrag has an OperandTransform EXTRACT_get_vextract{128,256}_imm, so the
index in $idx goes through the same conversion.

The existing test CodeGen/X86/avx512-insert-extract.ll extended in the
previous commit provides coverage for this change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218480 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 23:48:49 +00:00
Adam Nemet
2f3ccfc257 [AVX512] Make vextract*x4/vinsert*x4 tests check for the index as well
Extend test so that it provides coverage for the next commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218479 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 23:48:47 +00:00
Adam Nemet
4007b30ede [AVX512] Refactor subvector extracts
No functional change.

These are now implemented as two levels of multiclasses heavily relying on the
new X86VectorVTInfo class.  The multiclass at the first level that is called
with float or int provides the 128 or 256 bit subvector extracts.  The second
level provides the register and memory variants and some more Pat<>s.

I've compared the td.expanded files before and after.  One change is that
ExeDomain for 64x4 is SSEPackedDouble now.  I think this is correct, i.e. a
bugfix.

(BTW, this is the change that was blocked on the recent tablegen fix.  The
class-instance values X86VectorVTInfo inside vextract_for_type weren't
properly evaluated.)

Part of <rdar://problem/17688758>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218478 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 23:48:45 +00:00
Adam Nemet
1973ffefcf [AVX512] Fix typo
F->I in VEXTRACTF32x4rr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218477 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 23:48:42 +00:00
Hal Finkel
2a7d068c49 Add SDAG TableGen definitions for BR_CC
Add SelectionDAG TableGen definitions for BR_CC so that targets can instruction-select
BR_CC using TableGen pattern matching.

Patch by deadal nix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218476 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 23:34:18 +00:00
Matt Arsenault
3011a602be R600: Fix some missing conversion testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218474 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 23:16:18 +00:00
Matt Arsenault
556ae0484a Remove duplicated RUN lines in middle of test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218473 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 23:16:14 +00:00
Bruno Cardoso Lopes
f4230250a1 [MachineSink+PGO] Teach MachineSink to use BlockFrequencyInfo
Machine Sink uses loop depth information to select between successors BBs to
sink machine instructions into, where BBs within smaller loop depths are
preferable.  This patch adds support for choosing between successors by using
profile information from BlockFrequencyInfo instead, whenever the information
is available.

Tested it under SPEC2006 train (average of 30 runs for each program); ~1.5%
execution speedup in average on x86-64 darwin.

<rdar://problem/18021659>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218472 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 23:14:26 +00:00
David Majnemer
5c1c055cb7 Object: Add range iterators for Archive children
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218471 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 22:56:54 +00:00
Nick Kledzik
2fe3200c6a [Support] Fix Format.h to build on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218467 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 21:00:38 +00:00
Nick Kledzik
e93da60ac4 [Support] Add type-safe alternative to llvm::format()
llvm::format() is somewhat unsafe. The compiler does not check that integer
parameter size matches the %x or %d size and it does not complain when a 
StringRef is passed for a %s.  And correctly using a StringRef with format() is  
ugly because you have to convert it to a std::string then call c_str().
 
The cases where llvm::format() is useful is controlling how numbers and
strings are printed, especially when you want fixed width output.  This
patch adds some new formatting functions to raw_streams to format numbers
and StringRefs in a type safe manner. Some examples:

   OS << format_hex(255, 6)        => "0x00ff"
   OS << format_hex(255, 4)        => "0xff"
   OS << format_decimal(0, 5)      => "    0"
   OS << format_decimal(255, 5)    => "  255"
   OS << right_justify(Str, 5)     => "  foo"
   OS << left_justify(Str, 5)      => "foo  "



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218463 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 20:30:58 +00:00
Anton Yartsev
f85d5cfbf6 Refactoring: raw pointer -> unique_ptr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218462 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 19:55:58 +00:00
Tom Stellard
8361c84894 ARM: Remove unneeded check for MI->hasPostISelHook()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218459 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 18:59:23 +00:00
Tom Stellard
bdaf056545 SelectionDAG: Remove #if NDEBUG from check for a post-isel hook
The InstrEmitter will skip the check of MI.hasPostISelHook()
before calling AdjustInstrPostInstrSelection() when NDEBUG
is not defined.

This was added in r140228, and I'm not sure if it is intentional or not,
but it is a likely source for bugs, because it means with
Release+Asserts builds you can forget to set the hasPostISelHook
flag on TableGen definitions and AdjustInstrPostInstrSelection() will
still be called.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218458 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 18:59:22 +00:00
Tom Stellard
29d48e6a49 R600/SI: Add support for global atomic add
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218457 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 18:30:26 +00:00
Robin Morisset
79826e015e Lower idempotent RMWs to fence+load
Summary:
I originally tried doing this specifically for X86 in the backend in D5091,
but it was rather brittle and generally running too late to be general.
Furthermore, other targets may want to implement similar optimizations.
So I reimplemented it at the IR-level, fitting it into AtomicExpandPass
as it interacts with that pass (which could not be cleanly done before
at the backend level).

This optimization relies on a new target hook, which is only used by X86
for now, as the correctness of the optimization on other targets remains
an open question. If it is found correct on other targets, it should be
trivial to enable for them.

Details of the optimization are discussed in D5091.

Test Plan: make check-all + a new test

Reviewers: jfb

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5422

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218455 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 17:27:43 +00:00
Aaron Ballman
837a7c094b Since the DisasmMemoryObject only operates on const data, it now only accepts a const data pointer. This silences a -Wcast-qual warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218454 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 14:02:43 +00:00
Sid Manning
733681d3bd Add missing attributes !cmp.[eq,gt,gtu] instructions.
These instructions do not indicate they are extendable or the
number of bits in the extendable operand.  Rename to match
architected names.  Add a testcase for the intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218453 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25 13:09:54 +00:00