Commit Graph

103576 Commits

Author SHA1 Message Date
Ed Maste
fe0b2279a8 DebugInfo: Use enum instead of unsigned
This makes debuging DebugInfo generation with LLDB a little more pleasant.

Differential Revision: http://reviews.llvm.org/D3626


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208202 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 12:49:08 +00:00
Daniel Sanders
b2d170d61b [mips] Continue splitting Instruction.Predicates into smaller lists and re-join them with !listconcat
Summary:
Move IsGP64bit into GPRPredicates, and IsFP64bit/NotFP64bit into FGRPredicates

No functional change (confirmed by diffing tablegen-erated files).

Depends on D3639

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3640

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208201 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 12:48:37 +00:00
James Molloy
2712c87cfe [ARM64-BE] Fix fast-isel, and add appropriate RUN lines to appropriate tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208200 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 12:33:55 +00:00
James Molloy
d93d214a67 [ARM64-BE] Fix variable-argument saving.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208199 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 12:33:48 +00:00
James Molloy
fca7f5c585 [ARM64-BE] Implement the lane-twiddling logic at AAPCS boundaries for big endian.
The AAPCS states that values passed in registers must have a value as though
they had been loaded with "LDR". LDR is equivalent to "LD1.64 vX.1D" - that is,
loading scalars to vector registers and loading 1-element vectors is equivalent.

The logic implemented here is to ensure that at all call boundaries and during
formal argument lowering all vectors are treated as their bitwidth-based floating
point scalar counterpart, which is always one of f64 or f128 (v2i32 -> f64,
v4i32 -> f128 etc). A BITCAST is inserted so that the appropriate REV will be
generated during code generation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208198 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 12:33:41 +00:00
Daniel Sanders
1caec99d5d [mips] Move IsFP64bit/NotFP64bit to the front of the AdditionalPredicates list
Summary:
This makes it easier to prove a more complicated change in the next commit
is non-functional.

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3639

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208197 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 12:27:46 +00:00
James Molloy
737c2ac4fc [ARM64-BE] Implement the crazy bitcast handling for big endian vectors.
Because we've canonicalised on using LD1/ST1, every time we do a bitcast
between vector types we must do an equivalent lane reversal.

Consider a simple memory load followed by a bitconvert then a store.
  v0 = load v2i32
  v1 = BITCAST v2i32 v0 to v4i16
       store v4i16 v2

In big endian mode every memory access has an implicit byte swap. LDR and
STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
is, they treat the vector as a sequence of elements to be byte-swapped.
The two pairs of instructions are fundamentally incompatible. We've decided
to use LD1/ST1 only to simplify compiler implementation.

LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
the original code sequence:  v0 = load v2i32

  v1 = REV v2i32                  (implicit)
  v2 = BITCAST v2i32 v1 to v4i16
  v3 = REV v4i16 v2               (implicit)
       store v4i16 v3

But this is now broken - the value stored is different to the value loaded
due to lane reordering. To fix this, on every BITCAST we must perform two
other REVs:

  v0 = load v2i32
  v1 = REV v2i32                  (implicit)
  v2 = REV v2i32
  v3 = BITCAST v2i32 v2 to v4i16
  v4 = REV v4i16
  v5 = REV v4i16 v4               (implicit)
       store v4i16 v5

This means an extra two instructions, but actually in most cases the two REV
instructions can be combined into one. For example:
  (REV64_2s (REV64_4h X)) === (REV32_4h X)

There is also no 128-bit REV instruction. This must be synthesized with an
EXT instruction.

Most bitconverts require some sort of conversion. The only exceptions are:
  a) Identity conversions -  vNfX <-> vNiX
  b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX

Even though there are hundreds of changed lines, I have a fairly high confidence
that they are somewhat correct. The changes to add two REV instructions per
bitcast were pretty mechanical, and once I'd done that I threw the resulting
.td at a script I wrote which combined the two REVs together (and added
an EXT instruction, for f128) based on an instruction description I gave it.

This was much less prone to error than doing it all manually, plus my brain
would not just have melted but would have vapourised.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208194 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 11:28:53 +00:00
James Molloy
1f890ce2dc [ARM64-BE] Predicate VLDR/VSTR for vectors as little-endian only. We must use LD1/ST1 on big-endian.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208193 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 11:28:45 +00:00
James Molloy
104629cc7c [ARM64-BE] Make big endian (scalar) argument passing work correctly.
This completes the port of r204814 (cpirker "AArch64_BE function argument
passing for ARM ABI") from AArch64 to ARM64, and fixes a bunch of issues
found during later development along the way. The biggest of these was
that the alignment fixup logic wasn't replicated into all the places it
should have been.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208192 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 11:28:36 +00:00
Stepan Dyatkovskiy
9b363106f3 MergeFunctions Pass, introduced total ordering among values.
This is a third patch of patch series that improves MergeFunctions
performance time from O(N*N) to O(N*log(N)).

This patch description:
Being comparing functions we need to compare values we meet at left and
right sides.
Its easy to sort things out for external values. It just should be
the same value at left and right.
But for local values (those were introduced inside function body)
we have to ensure they were introduced at exactly the same place,
and plays the same role.

In short, patch introduces values serial numbering and comparison routine.
The last one compares two values by their serial numbers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208189 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 11:11:39 +00:00
Tim Northover
0d427515b3 AArch64/ARM64: run test on ARM64 too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208188 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 10:47:04 +00:00
Tim Northover
5a1d5139b8 AArch64/ARM64: put annotation in test
It makes finding already covered tests much easier with "grep -L
arm64".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208187 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 10:47:00 +00:00
Tim Northover
c6f683627d AArch64/ARM64: disable test directory if ARM64 not present
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208186 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 10:42:06 +00:00
Daniel Sanders
a3953a30b6 [mips] Split Instruction.Predicates into smaller lists and re-join them with !listconcat
Summary:
The overall idea is to chop the Predicates list into subsets that are
usually overridden independently. This allows subclasses to partially
override the predicates of their superclasses without having to re-add all
the existing predicates.

This patch starts the process by moving HasStdEnc into a new
EncodingPredicates list and almost everything else into
AdditionalPredicates.

It has revealed a couple likely bugs where 'let Predicates' has removed
the HasStdEnc predicate.

No functional change (confirmed by diffing tablegen-erated files).

Depends on D3549, D3506

Reviewers: vmedic

Differential Revision: http://reviews.llvm.org/D3550

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208184 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 10:27:09 +00:00
Daniel Sanders
d80222a48b [tablegen] Add !listconcat operator with the similar semantics as !strconcat
Summary:
It concatenates two or more lists. In addition to the !strconcat semantics
the lists must have the same element type.

My overall aim is to make it easy to append to Instruction.Predicates
rather than override it. This can be done by concatenating lists passed as
arguments, or by concatenating lists passed in additional fields.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: hfinkel, llvm-commits

Differential Revision: http://reviews.llvm.org/D3506

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208183 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 10:13:19 +00:00
Daniel Sanders
0c9ea21554 [mips] Move HasStdEnc to the front of the predicates lists.
Summary:
This will make it easier to prove that a more complicated change in the
following commit is non-functional.

No functional change.

Depends on D3506

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3549

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208179 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 09:58:05 +00:00
Zinovy Nis
6a48f1c271 [BUG][REFACTOR]
1) Fix for printing debug locations for absolute paths.
2) Location printing is moved into public method DebugLoc::print() to avoid re-inventing the wheel.

Differential Revision: http://reviews.llvm.org/D3513




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208177 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 09:51:22 +00:00
Stepan Dyatkovskiy
cb3a147870 Second patch of patch series that improves MergeFunctions performance time from O(N*N) to
O(N*log(N)). The idea is to introduce total ordering among functions set.
It allows to build binary tree and perform function look-up procedure in O(log(N)) time. 

This patch description:
Introduced total ordering among constants implemented in cmpConstants method.
Method performs lexicographical comparison between constants represented as
hypothetical numbers of next format:
<bitcastability-trait><raw-bit-contents>

Please, read cmpConstants declaration comments for more details.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208173 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 09:05:10 +00:00
Timur Iskhodzhanov
88ab50c237 Work-around MSVS build breakage due to r208148
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208171 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 08:52:13 +00:00
Evgeniy Stepanov
227c4c6185 [asan] Add a flag to control asm instrumentation.
With this change, asm instrumentation is disabled by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208167 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 07:54:11 +00:00
Joerg Sonnenberger
2ecdcdc026 Allow using normal .eh_frame based unwinding on ARM. Use the same
encodings as x86. Use this exception model for NetBSD.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208166 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 07:49:34 +00:00
David Blaikie
8a25ee1440 PR19562: DebugInfo temporary MDNode leak: Don't include a temporary node to replace with a variable list for methods, since they're always declarations and thus never include variables
This field is used for a list of variables to ensure they are not lost
during optimization (they're only included when optimizations are
enabled).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208159 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 06:08:28 +00:00
Tobias Grosser
a1f8bd6753 [C++11] Add NArySCEV->Operands iterator range
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208158 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 06:07:47 +00:00
Simon Atanasyan
111454f4e9 [obj2yaml] Recognize input file format using llvm::object::ObjectFile
interface methods isCOFF().

The '-coff' command line option has been removed. It was not used in any
test cases.

The patch reviewed by Michael Spencer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208157 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 05:18:51 +00:00
Saleem Abdulrasool
3fe09b705c ARM: mark additional instructions as MachineFrameSetup
Mark up additional instructions which are part of the function prologue as
MachineFrameSetup.  These instructions are part of the function prologue,
emitted by the PEI pass to setup the stack for use in the activating frame.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208153 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 03:03:31 +00:00
Saleem Abdulrasool
0029e2d665 ARM: fix WoA PEI instruction selection
The ARM::BLX instruction is an ARM mode instruction.  The Windows on ARM target
is limited to Thumb instructions.  Correctly use the thumb mode tBLXr
instruction.  This would manifest as an errant write into the object file as the
instruction is 4-bytes in length rather than 2.  The result would be a corrupted
object file that would eventually result in an executable that would crash at
runtime.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208152 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 03:03:27 +00:00
Justin Bogner
ffb8718ee5 llvm-cov: Document --no-output in the command guide
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208151 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 02:33:58 +00:00
Justin Bogner
c92330c18c llvm-cov: Handle missing source files as GCOV does
If the source files referenced by a gcno file are missing, gcov
outputs a coverage file where every line is simply /*EOF*/.  This also
occurs for lines in the coverage that are past the end of a file that
is found.

This change mimics gcov.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208149 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 02:11:23 +00:00
Justin Bogner
56d05e468c llvm-cov: Implement --no-output
In gcov, there's a -n/--no-output option, which disables the writing
of any .gcov files, so that it emits only the summary info on stdout.
This implements the same behaviour in llvm-cov.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208148 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 02:11:18 +00:00
Argyrios Kyrtzidis
6d46f2d394 [Support/MemoryBuffer] Remove the assertion that the file size did not shrink.
This can happen in practice with the user changing files and we can recover from it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208143 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 23:30:56 +00:00
Nico Weber
9e9ec9b69c Fix ASan init function detection after clang r208128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208141 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 23:17:26 +00:00
Rafael Espindola
26668d093e Special case aliases in GlobalValue::getSection.
This is similar to the getAlignment patch, but is done just for
completeness. It looks like we never call getSection on an alias. All the
tests still pass if the if is replaced with an assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208139 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 22:44:30 +00:00
Andrew Trick
8abb75bc61 Update an embarassing out-of-date comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208137 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 22:18:43 +00:00
Eric Christopher
887ab99a6e Use a range based for loop for the SubtargetFeatures print function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208132 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 21:20:29 +00:00
David Blaikie
ccad744d4a Revert "Try simplifying LexicalScopes ownership again."
Speculatively reverting due to a suspicious failure on a Windows
buildbot.

This reverts commit 10c37a012e.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208131 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 21:07:17 +00:00
Eric Christopher
d2ba53bdaa Fix odd formatting that snuck into last patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208130 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 21:04:27 +00:00
Joerg Sonnenberger
b84f890bc3 If a function needs a frame pointer, but r11 (aka fp) has not been used,
remove it from the list of unspilled registers. Otherwise the following
attempt to keep the stack aligned by picking an extra GPR register to
spill will not work as it picks up r11.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208129 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 20:43:01 +00:00
Eric Christopher
d474181920 ArrayRef-ize the Feature and Processor tables for SubtargetFeatures.
This removes arguments passed everywhere and allows the use of
standard iteration over lists.
Should be no functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208127 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 20:23:04 +00:00
Reid Kleckner
3949749701 Copy the full TailCallKind in CallInst::clone_impl
Split from the musttail inliner change.  This will be covered by an opt
test when the inliner change lands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208126 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 20:08:20 +00:00
Diego Novillo
e3e870face Do not make -pass-remarks additive.
Summary:
When I initially introduced -pass-remarks, I thought it would be a
neat idea to make it additive. So, if one used it as:

$ llc -pass-remarks=inliner --pass-remarks=loop.*

the compiler would build the regular expression '(inliner)|(loop.*)'.

The more I think about it, the more I regret it. This is not how
other flags work. The standard semantics are right-to-left overrides.

This is how clang interprets -Rpass. And I think the two should be
compatible in this respect.

Reviewers: qcolombet

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3614

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208122 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 19:14:00 +00:00
Benjamin Kramer
2c06cd8612 TTI: Estimate @llvm.fmuladd cost as fmul + fadd when FMA's aren't legal on the target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208115 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 18:36:23 +00:00
Andrea Di Biagio
8a712ba229 [X86] Improve the lowering of BITCAST dag nodes from type f64 to type v2i32 (and vice versa).
Before this patch, the backend always emitted a store+load sequence to
bitconvert from f64 to i64 the input operand of a ISD::BITCAST dag node that
performed a bitconvert from type MVT::f64 to type MVT::v2i32. The resulting
i64 node was then used to build a v2i32 vector.

With this patch, the backend now produces a cheaper SCALAR_TO_VECTOR from
MVT::f64 to MVT::v2f64. That SCALAR_TO_VECTOR is then followed by a "free"
bitcast to type MVT::v4i32. The elements of the resulting
v4i32 are then extracted to build a v2i32 vector (which is illegal and
therefore promoted to MVT::v2i64).

This is in general cheaper than emitting a stack store+load sequence
to bitconvert the operand from type f64 to type i64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208107 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 17:09:03 +00:00
Renato Golin
22f779d1fd Implememting named register intrinsics
This patch implements the infrastructure to use named register constructs in
programs that need access to specific registers (bare metal, kernels, etc).

So far, only the stack pointer is supported as a technology preview, but as it
is, the intrinsic can already support all non-allocatable registers from any
architecture.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208104 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 16:51:25 +00:00
Rafael Espindola
b889448841 Special case aliases in GlobalValue::getAlignment.
An alias has the address of what it points to, so it also has the same
alignment.

This allows a few optimizations to see past aliases for free.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208103 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 16:48:58 +00:00
Eric Christopher
bfc3f301b6 Have the SubtargetFeature help routine just not return a number and
fall back to the normal path without a cpu. While doing this fix
llc to just exit when we don't have a module to process instead of
asserting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208102 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 16:29:50 +00:00
Bob Wilson
534ec26d07 Add some details to the llvm-cov documentation. <rdar://problem/15819496>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208098 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 15:58:06 +00:00
Rafael Espindola
4f1723522e Be more strict about not allowing setSection on aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208095 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 14:59:14 +00:00
Rafael Espindola
55ba6a126f Be more strict about not calling setAlignment on global aliases.
The fact that GlobalAlias::setAlignment exists at all is a side effect of
how the classes are organized, it should never be used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208094 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 14:51:36 +00:00
Tim Northover
3524723195 AArch64/ARM64: implement diagnosis of unpredictable loads & stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208091 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 14:15:14 +00:00
Tim Northover
4d28f030f7 AArch64/ARM64: add two more MC tests to ARM64 set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208085 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 12:50:58 +00:00