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18181 Commits

Author SHA1 Message Date
Chris Lattner
8ceb0fd2d3 make a new missing features section 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35637 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 23:41:34 +00:00
Evan Cheng
ed884f3a2f Remove unused constant pool entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35635 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 23:39:48 +00:00
Bill Wendling
92ca81601c Updated 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35634 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 23:37:20 +00:00
Chris Lattner
7305084156 Fix a bug I introduced with my patch yesterday which broke Qt (I converted 
some constant exprs to apints).

Thanks to Anton for tracking down a small testcase that triggered this!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35633 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 23:29:39 +00:00
Chris Lattner
ef4c916193 greatly reduce hte default size of stringmap. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35632 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 22:15:38 +00:00
Evan Cheng
b03eacdbf3 Fixed a bug that causes codegen of noop like add r0, r0, #0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35627 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 21:31:21 +00:00
Chris Lattner
01deb9d91c reinstate the previous two patches, with a bugfix :) 
ldecod now passes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35626 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 17:43:25 +00:00
Nicolas Geoffray
0111999a88 Starting implementation of the ELF32 ABI specification of varargs handling. 
LowerVASTART emits the right code if the subtarget is ELF32, the other intrinsics
(VAARG, VACOPY and VAEND) are not yet implemented.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35625 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 13:59:52 +00:00
Nicolas Geoffray
ec58d9f9dd The PPC64 ELF ABI is "intended to use the same structure layout and calling convention rules 
as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/).
Change all ELF tests to ELF32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35624 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 12:35:28 +00:00
Nicolas Geoffray
cfcd8da70b Addition to the previous commit for getCalleeSavedRegClasses: 
"The ELF ABI specifies F1-F8 registers as argument registers for double, not
F1-F10. This affects only ELF, not MachO."


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35623 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 10:57:49 +00:00
Nicolas Geoffray
ef3c030e0e The ELF ABI specifies F1-F8 registers as argument registers for double, not 
F1-F10. This affects only ELF, not MachO.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35622 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 10:27:07 +00:00
Evan Cheng
d89f41e9bb Reverting back to 1.723. The last two commits broke JM (and possibily others) on ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35620 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 08:11:50 +00:00
Evan Cheng
3c5ad82ba2 Inverted logic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35619 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 06:44:25 +00:00
Evan Cheng
595b6d121c Bad bad bug. findRegisterUseOperand() returns -1 if a use if not found. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35618 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 06:43:29 +00:00
Bill Wendling
c9c9d2d554 Changed to new MMX_ recipes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35617 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 06:18:31 +00:00
Bill Wendling
823efee633 Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35616 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 06:00:37 +00:00
Chris Lattner
aed01d1931 split some code out into a helper function 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35615 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 05:11:24 +00:00
Chris Lattner
01d8c107ac Split a whole ton of code out of visitICmpInst into visitICmpInstWithInstAndIntCst. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35614 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 04:46:52 +00:00
Chris Lattner
44ad43033e Fix PR1253 and xor2.ll:test[01] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35612 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 01:47:41 +00:00
Chris Lattner
b2c594f350 Arm supports negative strides as well, add them. This lets us compile: 
CodeGen/ARM/arm-negative-stride.ll to:

LBB1_2: @bb
        str r1, [r3, -r0, lsl #2]
        add r0, r0, #1
        cmp r0, r2
        bne LBB1_2      @bb


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35609 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 00:13:57 +00:00
Chris Lattner
1d31290634 allow -1 strides to reuse "1" strides. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35607 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 22:51:58 +00:00
Scott Michel
c9dc114578 1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL. 
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35605 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 21:36:32 +00:00
Dale Johannesen
d959aa421a fix off by 1 error in displacement computation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35602 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 20:31:06 +00:00
Chris Lattner
6e0784da77 fix the CodeGen/ARM/2007-03-13-InstrSched.ll regression: allow IV's with scales 
to be folded into non-store instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35601 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 18:51:18 +00:00
Evan Cheng
bcfd4665b5 Ugh. Copy coalescer does not update register numbers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35600 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 18:49:18 +00:00
Chris Lattner
c4e3f8e736 add support for the 'w' inline asm register class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35598 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 17:24:08 +00:00
Zhou Sheng
4a1822a6d8 1. Make use of APInt operation instead of using ConstantExpr::getXXX. 
2. Use cheaper APInt methods.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35594 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 13:45:30 +00:00
Zhou Sheng
4351c649b2 Use uint32_t for bitwidth instead of unsigned. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35593 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 08:20:41 +00:00
Chris Lattner
1ebd89eb6b Pass the type of the store access, not the type of the store, into the 
target hook.  This allows us to codegen a loop as:

LBB1_1: @cond_next
        mov r2, #0
        str r2, [r0, +r3, lsl #2]
        add r3, r3, #1
        cmn r3, #1
        bne LBB1_1      @cond_next

instead of:

LBB1_1: @cond_next
        mov r2, #0
        str r2, [r0], #+4
        add r3, r3, #1
        cmn r3, #1
        bne LBB1_1      @cond_next

This looks the same, but has one fewer induction variable (and therefore,
one fewer register) live in the loop.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35592 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 06:34:44 +00:00
Chris Lattner
aa43e9f73b Fix a bug which caused us to never be able to use signed comparisons for 
equality comparisons of a constant.  This allows us to codegen the 'sintzero'
loop in PR1288 as:

LBB1_1: ;cond_next
        li r4, 0
        addi r2, r2, 1
        stw r4, 0(r3)
        addi r3, r3, 4
        cmpwi cr0, r2, -1
        bne cr0, LBB1_1 ;cond_next

instead of:

LBB1_1: ;cond_next
        addi r2, r2, 1
        li r4, 0
        xoris r5, r2, 65535
        stw r4, 0(r3)
        addi r3, r3, 4
        cmplwi cr0, r5, 65535
        bne cr0, LBB1_1 ;cond_next

This implements CodeGen/PowerPC/compare-simm.ll, and also cuts 74
instructions out of kc++.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35590 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 05:59:42 +00:00
Chris Lattner
cd1d6d5b03 Wrap long line 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35588 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 05:48:58 +00:00
Chris Lattner
acf4e074a9 use more obvious function name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35587 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 05:42:22 +00:00
Chris Lattner
2811f2a670 Treat xor of signbit like an add. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35586 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 05:41:38 +00:00
Chris Lattner
5c6e2db0c4 simplify (x+c)^signbit as (x+c+signbit), pointed out by PR1288. This implements 
test/Transforms/InstCombine/xor.ll:test28


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35584 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 05:36:22 +00:00
Chris Lattner
c995123182 reduce use of std::set 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35576 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 01:44:59 +00:00
Chris Lattner
d9c3a0d7cc Various passes before isel split edges and do other CFG-restructuring changes. 
isel has its own particular features that it wants in the CFG, in order to
reduce the number of times a constant is computed, etc.  Make sure that we
clean up the CFG before doing any other things for isel.  Doing so can
dramatically reduce the number of split edges and reduce the number of
places that constants get computed.  For example, this shrinks
CodeGen/Generic/phi-immediate-factoring.ll from 44 to 37 instructions on X86,
and from 21 to 17 MBB's in the output.  This is primarily a code size win,
not a performance win.

This implements CodeGen/Generic/phi-immediate-factoring.ll and PR1296.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35575 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 01:35:34 +00:00
Lauro Ramos Venancio
9996663fc6 - Divides the comparisons in two types: comparisons that only use N and Z 
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35573 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 01:30:03 +00:00
Reid Spencer
dc1966e6ba For PR1297: 
Make sure that the CTPOP result is casted to i32 as the bit counting
intrinsics all return i32 now (this affects CTLZ and CTTZ as well).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35567 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 01:01:49 +00:00
Chris Lattner
fe35555d09 print the type of an inserted IV in -debug mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35563 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-01 22:21:39 +00:00
Chris Lattner
55fc8c4c39 simplify this code, make it work for ap ints 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35561 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-01 20:57:36 +00:00
Chris Lattner
3e9f1d09c0 fix breakage from last night, simplify code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35560 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-01 20:49:36 +00:00
Reid Spencer
e613555fd9 The bit counting intrinsics return i32 not the operand type. This fixes 
last night's regression in SingleSource/UnitTests/2005-05-11-Popcount-ffs-fls


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35556 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-01 18:42:20 +00:00
Zhou Sheng
3a507fda84 Avoid unnecessary APInt construction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35555 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-01 17:13:37 +00:00
Evan Cheng
3074d9df96 Add i16 address mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35551 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-01 08:06:46 +00:00
Reid Spencer
e9391fd9b5 For PR1297: 
Support overloaded intrinsics bswap, ctpop, cttz, ctlz.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35547 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-01 07:35:23 +00:00
Reid Spencer
a4f9c4d29a For PR1297: 
Adjust for changes in the bit counting intrinsics. They all return i32
now so we have to trunc/zext the DAG node accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35546 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-01 07:34:11 +00:00
Reid Spencer
577cc32d9a For PR1297: 
Change getOperationName to return std::string instead of const char*


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35545 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-01 07:32:19 +00:00
Reid Spencer
1437a09765 For PR1297: 
Implement "actual" argument types for the Intrinsic member functions. This
involves changing the getName, getType, and getDeclaration methods to have
optional parameters for the actual types. These are necessary in order for
the type/name to be constructed properly for overloaded intrinsics. Only
the caller knows the actual argument types desired.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35541 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-01 07:25:33 +00:00
Reid Spencer
559d77afb3 For PR1297: 
1. Clear up confusion between "GotBits" and "ExpectBits". GotBits is the
   type actually provided. ExpectedBits is the type expected for the
   intrinsics. Before this patch, it was reversed!
2. Implement checks for overloaded intrinsics. This involves computing the
   suffix expected and making sure the suffix matches the function name. It
   also includes some intrinsic-specific checks such as ensuring that the
   bswap parameter and result are the same width and an even number of bytes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35540 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-01 07:22:57 +00:00
Chris Lattner
6abbdf90dd Fix InstCombine/2007-03-31-InfiniteLoop.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35536 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-01 05:36:37 +00:00