Commit Graph

72 Commits

Author SHA1 Message Date
Chris Lattner
751d5aa1ea constize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-14 22:33:49 +00:00
Chris Lattner
4766132036 clean up a bunch of code, move some random predicates
on TreePatternNode to be methods on TreePatternNode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96197 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-14 22:22:58 +00:00
Chris Lattner
523f6a5848 tidy up
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96186 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-14 21:10:15 +00:00
Bill Wendling
7529ece7af Use the 'MadeChange' variable instead of returning 'false' all of the time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92155 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-25 13:35:40 +00:00
Anton Korobeynikov
3a639a07ea Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364.
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85766 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 00:11:39 +00:00
Bob Wilson
cdfa01bf0f PR4795: Remove EEVT::isFP, isInt and isVec types used by TableGen's type
inferencing.  As far as I can tell, these are equivalent to the existing
MVT::fAny, iAny and vAny types, and having both of them makes it harder
to reason about and modify the type inferencing code.

The specific problem in PR4795 occurs when updating a vAny type to be fAny
or iAny, or vice versa.  Both iAny and fAny include vector types -- they
intersect with the set of types represented by vAny.  When merging them,
choose fAny/iAny to represent the intersection.  This is not perfect, since
fAny/iAny also include scalar types, but it is good enough for TableGen's
type inferencing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80423 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-29 05:53:25 +00:00
Benjamin Kramer
5b9e7ef627 Try to fix MSVC build after r79846.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79850 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-23 10:39:21 +00:00
Daniel Dunbar
6f5cc82686 Fix non-determinism in DAGISel emitter.
- This manifested as non-determinism in the .inc output in rare cases (when two
   distinct patterns ended up being equivalent, which is rather rare). That
   meant the pattern matching was non-deterministic, which could eventually mean
   the code generator selected different instructions based on the arch.

 - It's probably worth making the DAGISel ensure a total ordering (or force the
   user to), but the simple fix here is to totally order the Record* maps based
   on a unique ID.

 - PR4672, PR4711.

Yay:
--
ddunbar@giles:~$ cat ~/llvm.obj.64/lib/Target/*/*.inc | shasum
d1099ff34b21459a5a3e7021c225c080e6017ece  -
ddunbar@giles:~$ cat ~/llvm.obj.ppc/lib/Target/*/*.inc | shasum
d1099ff34b21459a5a3e7021c225c080e6017ece  -
--

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79846 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-23 09:47:37 +00:00
Chris Lattner
569f121f4e remove some DOUTs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79821 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-23 04:44:11 +00:00
Bob Wilson
36e3e668be Add a new "SDTCisVec" SDTypeConstraint. This complements the vAny type.
There have been a few times where I've wanted this but ended up leaving the
operand type unconstrained.  It is easy to add this now and should help
catch errors in the future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78849 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-12 22:30:59 +00:00
Owen Anderson
825b72b057 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 20:47:22 +00:00
Bob Wilson
61fc4cf7aa Add a new overloaded EVT::vAny type for use in TableGen to allow intrinsic
arguments that are vectors of any size and element type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78631 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 01:14:02 +00:00
Owen Anderson
e50ed30282 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 22:56:29 +00:00
Chris Lattner
a938ac6223 make ptr_rc derive from a new PointerLikeRegClass tblgen class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77503 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29 20:43:05 +00:00
Daniel Dunbar
1a55180238 Replace std::iostreams with raw_ostream in TableGen.
- Sorry, I can't help myself.

 - No intended functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74742 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03 00:10:29 +00:00
Evan Cheng
c0ad80fd9e Fix a CodeGenDAGPatterns bug. Check if top level predicates match when it's looking for duplicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74276 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 05:59:16 +00:00
Nick Lewycky
fc4c255304 Fix grammaro, and bad indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73602 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 04:23:52 +00:00
Bill Wendling
ee1f6b0fc5 I'm going to assume that this was meant to be an assignment instead of a
computation that isn't used. Please correct this if it's wrong!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73139 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-09 18:49:42 +00:00
David Greene
ffc0ab6037 Revert 73074 and 73099 because Windows doesn't have POSIX
regular expressions.  We will add an OpenBSD implementation
and re-apply ASAP.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73138 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-09 18:31:17 +00:00
David Greene
0d973999f3 Add a !patsubst operator. Use on string types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73099 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 23:05:37 +00:00
David Greene
e1b469170b Make IntInits and ListInits typed. This helps deduce types of !if and
other operators.  For the rare cases where a list type cannot be
deduced, provide a []<type> syntax, where <type> is the list element
type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73078 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 20:23:18 +00:00
Dale Johannesen
874ae251c3 Revert 72707 and 72709, for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02 03:12:52 +00:00
Dale Johannesen
4150d83abe Make the implicit inputs and outputs of target-independent
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag.  Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.

Most targets will still produce a Flag-setting target-dependent
version when selection is done.  X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc.  This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted.  All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly.  The
same can be done on other targets.

The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72707 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-01 23:27:20 +00:00
Nate Begeman
9008ca6b6b 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
PR2957

ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask.  A value of -1 represents UNDEF.

In addition to eliminating the creation of illegal BUILD_VECTORS just to 
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70225 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27 18:41:29 +00:00
Rafael Espindola
15684b2955 Revert 69952. Causes testsuite failures on linux x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69967 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-24 12:40:33 +00:00
Nate Begeman
b706d29f9c PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask.  A value of -1 represents UNDEF.

In addition to eliminating the creation of illegal BUILD_VECTORS just to 
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.

A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69952 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-24 03:42:54 +00:00
Dan Gohman
88c7af096b Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize
it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 21:06:25 +00:00
Dan Gohman
f8c7394781 Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.
This will be used to replace things like X86's MOV32to32_.

Enhance ScheduleDAGSDNodesEmit to be more flexible and robust
in the presense of subregister superclasses and subclasses. It
can now cope with the definition of a virtual register being in
a subclass of a use.

Re-introduce the code for recording register superreg classes and
subreg classes. This is needed because when subreg extracts and
inserts get coalesced away, the virtual registers are left in
the correct subclass.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 15:38:05 +00:00
Dan Gohman
4b6fce4c05 Tidy up some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68112 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-31 16:48:35 +00:00
Jim Grosbach
da4231f134 fix a few spelling errors and typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67758 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-26 16:17:51 +00:00
Nate Begeman
7cee81703d Add support to tablegen for naming the nodes themselves, not just the operands,
in selectiondag patterns.  This is required for the upcoming shuffle_vector rewrite,
and as it turns out, cleans up a hack in the Alpha instruction info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67286 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-19 05:21:56 +00:00
Chris Lattner
a14b1ded69 add a new TGError class and use it to propagate location info with
errors when thrown.  This gets us nice errors like this from tblgen:

CMOVL32rr: 	(set GR32:i32:$dst, (X86cmov GR32:$src1, GR32:$src2))
/Users/sabre/llvm/Debug/bin/tblgen: error:
Included from X86.td:116:
Parsing X86InstrInfo.td:922: In CMOVL32rr: X86cmov node requires exactly 4 operands!
def CMOVL32rr : I<0x4C, MRMSrcReg,       // if <s, GR32 = GR32
^

instead of just:

CMOVL32rr: 	(set GR32:i32:$dst, (X86cmov GR32:$src1, GR32:$src2))
/Users/sabre/llvm/Debug/bin/tblgen: In CMOVL32rr: X86cmov node requires exactly 4 operands!

This is all I plan to do with this, but it should be easy enough to improve if anyone 
cares (e.g. keeping more loc info in "dag" expr records in tblgen.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66898 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13 16:25:21 +00:00
Dale Johannesen
49de98214b Reapply 63765. Patches for clang and llvm-gcc to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63812 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-05 01:49:45 +00:00
Dale Johannesen
4d452de150 Reverting 63765. This broke the build of both clang
and llvm-gcc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63786 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-04 22:47:25 +00:00
Nate Begeman
d24479730a New feature: add support for target intrinsics being defined in the
target directories themselves.  This also means that VMCore no longer
needs to know about every target's list of intrinsics.  Future work
will include converting the PowerPC target to this interface as an
example implementation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63765 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-04 19:47:21 +00:00
Duncan Sands
b0d5cdd52e Fix PR3453 and probably a bunch of other potential
crashes or wrong code with codegen of large integers:
eliminate the legacy getIntegerVTBitMask and
getIntegerVTSignBit methods, which returned their
value as a uint64_t, so couldn't handle huge types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63494 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-01 18:06:53 +00:00
Bob Wilson
e035fa50f3 Handle iAny and fAny types in TreePatternNode::UpdateNodeType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61713 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-05 17:52:54 +00:00
Bob Wilson
6c01ca9e29 Fix spelling in some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61702 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-05 17:23:09 +00:00
Dan Gohman
62c939d7d5 Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's
foldMemoryOperand how to "fold" them, by converting them into constant-pool
loads. When they aren't folded, they use xorps/cmpeqd, but for example when
register pressure is high, they may now be folded as memory operands, which
reduces register pressure.

Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will
remat it instead of copying zeros around (V_SETALLONES was already marked).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60461 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03 05:21:24 +00:00
Dan Gohman
41474baac8 Add a sanity-check to tablegen to catch the case where isSimpleLoad
is set but mayLoad is not set. Fix all the problems this turned up.

Change code to not use isSimpleLoad instead of mayLoad unless it
really wants isSimpleLoad.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60459 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03 02:30:17 +00:00
Bill Wendling
cdcc3e6e12 Modify the intrinsics pattern to separate out the "return" types from the
"parameter" types. An intrinsic can now return a multiple return values like
this:

  def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty],
                                    [LLVMMatchType<0>, LLVMMatchType<0>]>;



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Dan Gohman
0540e17788 Add support for having multiple predicates on a TreePatternNode.
This will allow predicates to be composed, which will allow the
predicate definitions to become less redundant, and eventually
will allow DAGISelEmitter.cpp to emit less redundant code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-15 06:17:21 +00:00
Dan Gohman
22bb31103d Factor out the predicate check code from DAGISelEmitter.cpp
and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55156 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-22 00:20:26 +00:00
Mon P Wang
e3b3a7241c Added support for overloading intrinsics (atomics) based on pointers
to different address spaces.  This alters the naming scheme for those
intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54195 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-30 04:36:53 +00:00
Chris Lattner
2ca698df93 check in anton's patch to make inlining happen in a determinstic order
and fix the bug that it uncovers: inlining a pattern fragment could bring
in other pattern fragments if the inlinee hadn't already been inlined.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52888 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-30 03:02:03 +00:00
Mon P Wang
2887310630 Added MemOperands to Atomic operations since Atomics touches memory.
Added abstract class MemSDNode for any Node that have an associated MemOperand
Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and
atomic.lss => atomic.load.sub


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52706 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-25 08:15:39 +00:00
Evan Cheng
6bd9567a6a - Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code.
- Mark lots of X86 intrinsics as "Commutative" to allow load folding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
Duncan Sands
83ec4b6711 Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-06 12:08:01 +00:00
Dan Gohman
e4c67cdab4 Teach the DAGISelEmitter to not compute the variable_ops operand
index for the input pattern in terms of the output pattern. Instead
keep track of how many fixed operands the input pattern actually
has, and have the input matching code pass the output-emitting
function that index value. This simplifies the code, disentangles
variables_ops from the support for predication operations, and
makes variable_ops more robust.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51808 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-31 02:11:25 +00:00
Dan Gohman
d35121ad00 Fix a tblgen problem handling variable_ops in tblgen instruction
definitions. This adds a new construct, "discard", for indicating
that a named node in the input matching pattern is to be discarded,
instead of corresponding to a node in the output pattern. This
allows tblgen to know where the arguments for the varaible_ops are
supposed to begin.

This fixes "rdar://5791600", whatever that is ;-).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51699 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 19:57:41 +00:00