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11 Commits

Author SHA1 Message Date
Tom Stellard
19cb35b4bc R600/SI: Start implementing an assembler 
This was done using the Sparc and PowerPC AsmParsers as guides.  So far it
is very simple and only supports sopp instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221994 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-14 14:08:00 +00:00
Vincent Lejeune
b3df27d440 R600: Use SchedModel enum for is{Trans,Vector}Only functions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189979 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-04 19:53:30 +00:00
Tom Stellard
8e78012457 R600: Add support for i8 and i16 local memory stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189223 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-26 15:05:49 +00:00
Tom Stellard
e7ac2ed1c2 R600: Add IsExport bit to TableGen instruction definitions 
Tested-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188516 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-16 01:11:51 +00:00
Tom Stellard
af2ea2a4fb Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions" 
This reverts commit 3f1de26cb5.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187524 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 20:43:03 +00:00
Vincent Lejeune
3f1de26cb5 R600: Use SchedModel enum for is{Trans,Vector}Only functions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187512 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 19:31:35 +00:00
Tom Stellard
e3d4cbc7d2 R600: Add local memory support via LDS 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185162 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-28 15:47:08 +00:00
Tom Stellard
7e9381951e R600: Add ALUInst bit to tablegen definitions v2 
v2:
  - Remove functions left over from a previous rebase.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185160 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-28 15:46:53 +00:00
Tom Stellard
d6055262d2 R600: Use correct encoding for Vertex Fetch instructions on Cayman 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184016 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-14 22:12:30 +00:00
Tom Stellard
c30b232349 R600: Factor the instruction encoding out the RAT_WRITE_CACHELESS_eg class 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184014 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-14 22:12:19 +00:00
Tom Stellard
2def95fc1e R600: Move instruction encoding definitions into a separate .td file 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184013 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-14 22:12:09 +00:00