4526 Commits

Author SHA1 Message Date
Andrew Trick
d427132a34 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180665 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-27 03:54:14 +00:00
Eric Christopher
00297bad0d Use the target triple from the target machine rather than the module
to determine whether or not we're on a darwin platform for debug code
emitting.

Solves the problem of a module with no triple on the command line
and no triple in the module using non-gdb ok features on darwin. Fix
up the member-pointers test to check the correct things for cross
platform (DW_FORM_flag is a good prefix).

Unfortunately no testcase because I have no ideas how to test something
without a triple and without a triple in the module yet check
precisely on two platforms. Ideas welcome.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180660 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-27 01:07:52 +00:00
Reid Kleckner
4b55815303 [mc-coff] Forward Linker Option flags into the .drectve section
Summary:
This is modelled on the Mach-O linker options implementation and should
support a Clang implementation of #pragma comment(lib/linker).

Reviewers: rafael

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D724

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 19:34:41 +00:00
Andrew Trick
e38afe1e33 MI Sched: eliminate local vreg copies.
For now, we just reschedule instructions that use the copied vregs and
let regalloc elliminate it. I would really like to eliminate the
copies on-the-fly during scheduling, but we need a complete
implementation of repairIntervalsInRange() first.

The general strategy is for the register coalescer to eliminate as
many global copies as possible and shrink live ranges to be
extended-basic-block local. The coalescer should not have to worry
about resolving local copies (e.g. it shouldn't attemp to reorder
instructions). The scheduler is a much better place to deal with local
interference. The coalescer side of this equation needs work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180193 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 15:54:43 +00:00
Andrew Trick
efa1458ef3 Comment a strange field in ScheduleDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180159 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23 23:45:08 +00:00
Eli Bendersky
2ad047e04d Optimize MachineBasicBlock::getSymbol by caching the symbol. Since the symbol
name computation is expensive, this helps save about 25% of the time spent in
this function.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180049 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22 21:21:08 +00:00
Eli Bendersky
8247c5df9c Fix comment that didn't match the method it was above
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180043 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22 20:30:50 +00:00
Rafael Espindola
cde25b435a Clarify that llvm.used can contain aliases.
Also add a check for llvm.used in the verifier and simplify clients now that
they can assume they have a ConstantArray.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180019 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22 14:58:02 +00:00
Tim Northover
6265d5c91a Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-20 12:32:17 +00:00
Eli Bendersky
462123f661 Simplify the code in FastISel::tryToFoldLoad, add an assertion and fix a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179908 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19 23:26:18 +00:00
Eli Bendersky
75299e3a95 Move TryToFoldFastISelLoad to FastISel, where it belongs. In general, I'm
trying to move as much FastISel logic as possible out of the main path in
SelectionDAGISel - intermixing them just adds confusion.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179902 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19 22:29:18 +00:00
Michael Liao
2a8bea7a8e ArrayRefize getMachineNode(). No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19 22:22:57 +00:00
Jakob Stoklund Olesen
a58d67af29 Add an MRI::verifyUseLists() function.
This checks the sanity of the register use lists in the MI intermediate
representation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179895 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19 21:40:57 +00:00
Lang Hames
64362272b6 Add support for index resources (for a SlotIndex) to be relinquished.
When the SlotIndexes pass was introduced it was intended to support insertion
of code during register allocation. Removal of code was a minor consideration
(and raised the question of what to do about dangling SlotIndex objects pointing
to the erased index), so I opted to keep all indexes around indefinitely and
simply null out those that weren't being used.

Nowadays people are moving more code around (e.g. via HandleMove), which means
more zombie indexes. I want to start killing off indexes when we're done with
them to reclaim the resources they use up.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179834 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19 04:31:49 +00:00
Arnold Schwaighofer
f971916768 Fix bit size of v64i8 and v32i16 vector types.
Patch by Cameron McInally <cameron.mcinally@nyu.edu>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179535 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 16:11:25 +00:00
Andy Gibbs
604b3573f9 Replace uses of the deprecated std::auto_ptr with OwningPtr.
This is a rework of the broken parts in r179373 which were subsequently reverted in r179374 due to incompatibility with C++98 compilers.  This version should be ok under C++98.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179520 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 12:06:32 +00:00
Andrew Trick
4392f0f407 MI-Sched: schedule physreg copies.
The register allocator expects minimal physreg live ranges. Schedule
physreg copies accordingly. This is slightly tricky when they occur in
the middle of the scheduling region. For now, this is handled by
rescheduling the copy when its associated instruction is
scheduled. Eventually we may instead bundle them, but only if we can
preserve the bundles as parallel copies during regalloc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179449 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13 06:07:40 +00:00
Benjamin Kramer
3389e10d67 Revert broken pieces of r179373.
You can't copy an OwningPtr, and move semantics aren't available in C++98.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179374 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12 12:13:51 +00:00
Andy Gibbs
200241e4de Replace uses of the deprecated std::auto_ptr with OwningPtr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179373 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12 10:56:28 +00:00
Benjamin Kramer
8f5836510a Use a real union for IdentifyingPassPtr.
This avoids a nasty const correctness issue (AnalysisIDs are const, Pass* isn't).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179213 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 20:50:44 +00:00
Andrew Trick
5ed028385c Generalize the PassConfig API and remove addFinalizeRegAlloc().
The target hooks are getting out of hand. What does it mean to run
before or after regalloc anyway? Allowing either Pass* or AnalysisID
pass identification should make it much easier for targets to use the
substitutePass and insertPass APIs, and create less need for badly
named target hooks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179140 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 01:06:56 +00:00
Hal Finkel
2e80991a77 Reapply r178845 with fix - Fix bug in PEI's virtual-register scavenging
This fixes PEI as previously described, but correctly handles the case where
the instruction defining the virtual register to be scavenged is the first in
the block. Arnold provided me with a bugpoint-reduced test case, but even that
seems too large to use as a regression test. If I'm successful in cleaning it
up then I'll commit that as well.

Original commit message:

    This change fixes a bug that I introduced in r178058. After a register is
    scavenged using one of the available spills slots the instruction defining the
    virtual register needs to be moved to after the spill code. The scavenger has
    already processed the defining instruction so that registers killed by that
    instruction are available for definition in that same instruction. Unfortunately,
    after this, the scavenger needs to iterate through the spill code and then
    visit, again, the instruction that defines the now-scavenged register. In order
    to avoid confusion, the register scavenger needs the ability to 'back up'
    through the spill code so that it can again process the instructions in the
    appropriate order. Prior to this fix, once the scavenger reached the
    just-moved instruction, it would assert if it killed any registers because,
    having already processed the instruction, it believed they were undefined.

    Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar
    for diagnosing the problem and testing this fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178919 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05 22:31:56 +00:00
Hal Finkel
b6cfeb63f8 Revert r178845 - Fix bug in PEI's virtual-register scavenging
Reverting because this breaks one of the LTO builders. Original commit message:

    This change fixes a bug that I introduced in r178058. After a register is
    scavenged using one of the available spills slots the instruction defining the
    virtual register needs to be moved to after the spill code. The scavenger has
    already processed the defining instruction so that registers killed by that
    instruction are available for definition in that same instruction. Unfortunately,
    after this, the scavenger needs to iterate through the spill code and then
    visit, again, the instruction that defines the now-scavenged register. In order
    to avoid confusion, the register scavenger needs the ability to 'back up'
    through the spill code so that it can again process the instructions in the
    appropriate order. Prior to this fix, once the scavenger reached the
    just-moved instruction, it would assert if it killed any registers because,
    having already processed the instruction, it believed they were undefined.

    Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar
    for diagnosing the problem and testing this fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178916 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05 21:30:40 +00:00
Hal Finkel
afe2f43e4e Fix bug in PEI's virtual-register scavenging
This change fixes a bug that I introduced in r178058. After a register is
scavenged using one of the available spills slots the instruction defining the
virtual register needs to be moved to after the spill code. The scavenger has
already processed the defining instruction so that registers killed by that
instruction are available for definition in that same instruction. Unfortunately,
after this, the scavenger needs to iterate through the spill code and then
visit, again, the instruction that defines the now-scavenged register. In order
to avoid confusion, the register scavenger needs the ability to 'back up'
through the spill code so that it can again process the instructions in the
appropriate order. Prior to this fix, once the scavenger reached the
just-moved instruction, it would assert if it killed any registers because,
having already processed the instruction, it believed they were undefined.

Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar
for diagnosing the problem and testing this fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178845 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05 05:01:13 +00:00
Jakob Stoklund Olesen
8396e13042 Count processor resources individually in MachineTraceMetrics.
The new instruction scheduling models provide information about the
number of cycles consumed on each processor resource. This makes it
possible to estimate ILP more accurately than simply counting
instructions / issue width.

The functions getResourceDepth() and getResourceLength() now identify
the limiting processor resource, and return a cycle count based on that.

This gives more precise resource information, particularly in traces
that use one resource a lot more than others.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178553 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02 17:49:51 +00:00
Benjamin Kramer
74a4533a42 Remove the old CodePlacementOpt pass.
It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178349 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 17:14:24 +00:00
Rafael Espindola
7fe65d691d Cleanup the simplify_type implementation.
As far as simplify_type is concerned, there are 3 kinds of smart pointers:

* const correct: A 'const MyPtr<int> &' produces a 'const int*'. A
'MyPtr<int> &' produces a 'int *'.
* always const: Even a 'MyPtr<int> &' produces a 'const int*'.
* no const: Even a 'const MyPtr<int> &' produces a 'int*'.

This patch then does the following:

* Removes the unused specializations. Since they are unused, it is hard
to know which kind should be implemented.
* Make sure we don't drop const.
* Fix the default forwarding so that const correct pointer only need
one specialization.
* Simplifies the existing specializations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178147 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27 16:43:11 +00:00
Hal Finkel
df23a60fa6 Fix the register scavenger for targets that provide custom spilling
As pointed out by Richard Sandiford, my recent updates to the register
scavenger broke targets that use custom spilling (because the new code assumed
that if there were no valid spill slots, than spilling would be impossible).

I don't have a test case, but it should be possible to create one for Thumb 1,
Mips 16, etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178073 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26 21:20:15 +00:00
Hal Finkel
8846129f6e Update PEI's virtual-register-based scavenging to support multiple simultaneous mappings
The previous algorithm could not deal properly with scavenging multiple virtual
registers because it kept only one live virtual -> physical mapping (and
iterated through operands in order). Now we don't maintain a current mapping,
but rather use replaceRegWith to completely remove the virtual register as
soon as the mapping is established.

In order to allow the register scavenger to return a physical register killed
by an instruction for definition by that same instruction, we now call
RS->forward(I) prior to eliminating virtual registers defined in I. This
requires a minor update to forward to ignore virtual registers.

These new features will be tested in forthcoming commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178058 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26 18:56:54 +00:00
Yiannis Tsiouris
477de3a785 Add a GC plugin for Erlang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177867 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 13:47:46 +00:00
Hal Finkel
dc3beb9017 Allow the register scavenger to spill multiple registers
This patch lets the register scavenger make use of multiple spill slots in
order to guarantee that it will be able to provide multiple registers
simultaneously.

To support this, the RS's API has changed slightly: setScavengingFrameIndex /
getScavengingFrameIndex have been replaced by addScavengingFrameIndex /
isScavengingFrameIndex / getScavengingFrameIndices.

In forthcoming commits, the PowerPC backend will use this capability in order
to implement the spilling of condition registers, and some special-purpose
registers, without relying on r0 being reserved. In some cases, spilling these
registers requires two GPRs: one for addressing and one to hold the value being
transferred.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22 23:32:27 +00:00
Hal Finkel
9b294d4056 Remove ScavengedRC from RegisterScavenging
ScavengedRC was a dead private variable (set, but not otherwise used). No
functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22 07:27:44 +00:00
Eric Christopher
9dff83dfb0 Remove blank line before block comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177550 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20 18:25:12 +00:00
Jakub Staszak
f31034db8c Move #include of BitVector from .h to .cpp file.
Also remove unneeded #include and forward declaration.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177357 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18 23:45:45 +00:00
Jakub Staszak
c2248b0e78 Add some constantness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177356 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18 23:40:46 +00:00
Hal Finkel
0cc52c67db Move estimateStackSize from ARM into MachineFrameInfo
This is a generic function (derived from PEI); moving it into
MachineFrameInfo eliminates a current redundancy between the ARM and AArch64
backends, and will allow it to be used by the PowerPC target code.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177111 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 21:15:20 +00:00
Eli Bendersky
6acbcd423b Residual cleanup: live-out set is gone
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176836 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11 23:18:25 +00:00
Jakub Staszak
760fa5dc80 Cleanup #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176787 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-10 13:11:23 +00:00
Jakub Staszak
03bf8fd288 Remove unneeded #include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176785 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-10 01:15:14 +00:00
Jakub Staszak
35d00e55dc Add some constantness in MachinePostDominators.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176784 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-10 01:14:42 +00:00
Jakub Staszak
d683edc711 Remove unneeded cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176776 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-09 19:34:14 +00:00
Jakob Stoklund Olesen
768ed8b8c3 No really, don't use end().
Clearly, this function is never actually called with the last
instruction in the function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 18:36:36 +00:00
Jakob Stoklund Olesen
e77b6ceb02 Avoid creating a SlotIndex from the end() iterator.
No test case, spotted by inspection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176705 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 18:08:54 +00:00
Jakob Stoklund Olesen
6ffcd5efe1 Rename isEarlierInSameTrace to isUsefulDominator.
In very rare cases caused by irreducible control flow, the dominating
block can have the same trace head without actually being part of the
trace.

As long as such a dominator still has valid instruction depths, it is OK
to use it for computing instruction depths.

Rename the function to avoid lying, and add a check that instruction
depths are computed for the dominator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176668 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-07 23:55:49 +00:00
Benjamin Kramer
3853f74aba ArrayRefize some code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176648 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-07 20:33:29 +00:00
Michael Liao
a6b20ced76 Fix PR10475
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands
  but TLI.getShiftAmountTy() so far only return scalar type. As a
  result, backend logic assuming that breaks.
- Rename the original TLI.getShiftAmountTy() to
  TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to
  return target-specificed scalar type or the same vector type as the
  1st operand.
- Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar
  type.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01 18:40:30 +00:00
Yiannis Tsiouris
081f4558cf GCInfoDeleter code cleanup after r175528
Remove GCInfoDeleter from passes and comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176347 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01 11:40:32 +00:00
Andrew Trick
ebff1d9035 Fix incorrect ScheduleDAG comment and formalize Weak edges.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176315 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01 00:19:12 +00:00
Eli Bendersky
6437d38a0d A small refactoring + adding comments.
SelectionDAGIsel::LowerArguments needs a function, not a basic block. So it
makes sense to pass it the function instead of extracting a basic-block from
the function and then tossing it. This is also more self-documenting (functions
have arguments, BBs don't).

In addition, added comments to a couple of Select* methods.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176305 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-28 23:09:18 +00:00
Michael Ilseman
7dbd34b199 Reverted: r176136 - Have a way for a target to opt-out of target-independent fast isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176204 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-27 19:54:00 +00:00