Commit Graph

110614 Commits

Author SHA1 Message Date
Peter Collingbourne
a1d9932027 Add target triples to all dfsan tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223536 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 22:32:30 +00:00
Kuba Brecka
0a12d8211e Recommit of r223513 and r223514.
Reviewed at http://reviews.llvm.org/D6488



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223532 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 22:19:18 +00:00
Colin LeMahieu
d2f12fd27a [Hexagon] Relocating logical instructions and templates later in the td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223523 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 21:51:12 +00:00
Colin LeMahieu
ec51bc6f3a [Hexagon] Adding sub/and/or reg, imm forms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223522 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 21:38:29 +00:00
Rafael Espindola
9423af6b70 Remove dead code. We are only lazy about functions with bodies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223521 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 21:36:06 +00:00
Kuba Brecka
05c096b953 Reverting r223513 and r223514.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223520 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 21:32:46 +00:00
Sanjay Patel
ab4ad4f98e Optimize merging of scalar loads for 32-byte vectors [X86, AVX]
Fix the poor codegen seen in PR21710 ( http://llvm.org/bugs/show_bug.cgi?id=21710 ).
Before we crack 32-byte build vectors into smaller chunks (and then subsequently
glue them back together), we should look for the easy case where we can just load
all elements in a single op.

An example of the codegen change is:

From:

vmovss  16(%rdi), %xmm1
vmovups (%rdi), %xmm0
vinsertps       $16, 20(%rdi), %xmm1, %xmm1
vinsertps       $32, 24(%rdi), %xmm1, %xmm1
vinsertps       $48, 28(%rdi), %xmm1, %xmm1
vinsertf128     $1, %xmm1, %ymm0, %ymm0
retq

To:

vmovups (%rdi), %ymm0
retq

Differential Revision: http://reviews.llvm.org/D6536



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223518 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 21:28:14 +00:00
Peter Collingbourne
93712874d8 [DFSAN][MIPS][LLVM] Defining ShadowPtrMask variable for MIPS64
Patch by Kumar Sukhani!

corresponding compiler-rt patch: http://reviews.llvm.org/D6437
clang patch: http://reviews.llvm.org/D6147

Differential Revision: http://reviews.llvm.org/D6459

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223516 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 21:22:32 +00:00
Colin LeMahieu
5db47f1376 [Hexagon] Updating mux_ir/ri/ii/rr with encoding bits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223515 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 21:09:27 +00:00
Kuba Brecka
86af53ecf0 AddressSanitizer - Don't instrument globals from cstring_literals sections. (llvm part)
Reviewed at http://reviews.llvm.org/D6488



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223513 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 21:04:43 +00:00
Rafael Espindola
f117c8ae03 Simplify the loop linking function bodies. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223512 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 21:04:36 +00:00
Jan Wen Voung
a44126f432 Use 32-bit ebp for NaCl64 in a limited case: llvm.frameaddress.
Summary:
Follow up to [x32] "Use ebp/esp as frame and stack pointer":
http://reviews.llvm.org/D4617

In that earlier patch, NaCl64 was made to always use rbp.
That's needed for most cases because rbp should hold a full
64-bit address within the NaCl sandbox so that load/stores
off of rbp don't require sandbox adjustment (zeroing the top
32-bits, then filling those by adding r15).

However, llvm.frameaddress returns a pointer and pointers
are 32-bit for NaCl64. In this case, use ebp instead, which
will make the register copy type check. A similar mechanism
may be needed for llvm.eh.return, but is not added in this change.

Test Plan: test/CodeGen/X86/frameaddr.ll

Reviewers: dschuff, nadav

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D6514

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223510 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 20:55:53 +00:00
Bill Seurer
8dcc5c0996 [PowerPC]Update Power VSX test cases to also test fast-isel
Update of some of the VSX test cases for Power to check fast-isel codegen as well as the regular codegen.

http://reviews.llvm.org/D6357


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223509 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 20:32:05 +00:00
Bill Seurer
dfa6293b55 [PowerPC]Add VSX loads/stores to fastisel for PPC target
This patch adds VSX floating point loads and stores to fastisel.

Along with the change to tablegen (D6220), VSX instructions are now fully supported in fastisel.

http://reviews.llvm.org/D6274


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223507 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 20:15:56 +00:00
Colin LeMahieu
4fda99f866 [Hexagon] Adding tfrih/l instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223506 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 20:07:19 +00:00
Andrea Di Biagio
6a9a49d7ab [X86] Improved lowering of packed vector shifts to vpsllq/vpsrlq.
SSE2/AVX non-constant packed shift instructions only use the lower 64-bit of
the shift count. 

This patch teaches function 'getTargetVShiftNode' how to deal with shifts
where the shift count node is of type MVT::i64.

Before this patch, function 'getTargetVShiftNode' only knew how to deal with
shift count nodes of type MVT::i32. This forced the backend to wrongly
truncate the shift count to MVT::i32, and then zero-extend it back to MVT::i64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223505 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 20:02:22 +00:00
Colin LeMahieu
189606dbfe [Hexagon] Adding add reg, imm form with encoding bits and test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223504 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 19:51:23 +00:00
Rafael Espindola
98821ee350 Remove unused arguments. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223503 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 19:35:07 +00:00
Eric Christopher
7a76d76e0c These two calls were grabbing the same register info. Unify them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223502 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 19:23:55 +00:00
Duncan P. N. Exon Smith
1a283409bc BFI: Saturate when combining edges to a successor
When a loop gets bundled up, its outgoing edges are quite large, and can
just barely overflow 64-bits.  If one successor has multiple incoming
edges -- and that successor is getting all the incoming mass --
combining just its edges can overflow.  Handle that by saturating rather
than asserting.

This fixes PR21622.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223500 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 19:13:42 +00:00
Colin LeMahieu
78ec9010c5 [Hexagon] Adding DoubleRegs decoder. Moving C2_mux and A2_nop. Adding combine imm-imm form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223494 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 18:24:06 +00:00
Adrian Prantl
33ada85735 Fix a bug when pretty-printing DW_OP_deref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223493 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 18:19:38 +00:00
Adrian Prantl
bb3e8dc693 Regenerate this stale testcase from source.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223492 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 18:19:32 +00:00
Ahmed Bougacha
bf6e012f8e [CodeGenPrepare] Use variables for reused values. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223491 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 18:04:40 +00:00
Colin LeMahieu
fba13406e2 [Hexagon] [NFC] Rearranging patterns and mux instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223488 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 17:58:06 +00:00
Colin LeMahieu
639b824b52 [Hexagon] [NFC] Rearranging def order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223487 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 17:55:51 +00:00
Rafael Espindola
24ba29981c Refactor duplicated code. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223486 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 17:53:15 +00:00
Colin LeMahieu
0785bdf107 [Hexagon] Adding combine reg-reg forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223485 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 17:38:36 +00:00
Colin LeMahieu
4c58675d35 [Hexagon] Marking several instructions as isCodeGenOnly=0 and adding direct disassembly tests for many instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223482 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 17:27:39 +00:00
Rafael Espindola
33f1a430c2 Be less conservative about when we build the gold plugin.
It is only build if LLVM_BINUTILS_INCDIR is explicitly given, so there is
no point in having extra restrictions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223481 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 17:25:52 +00:00
Benjamin Kramer
472e9cc4bc LLVMContext: Store APInt/APFloat directly into the ConstantInt/FP DenseMaps.
Required some APInt massaging to get proper empty/tombstone values. Apart
from making the code a bit simpler this also reduces the bucket size of
the ConstantInt map from 32 to 24 bytes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223478 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 17:03:01 +00:00
Asiri Rathnayake
3ad762170b Improvements to ARM assembler tests
No functional changes. Got myself bitten in r223113 when adding support for
modified immediate syntax (regressions reported by joerg@britannica.bec.de,
fixes in r223366 and r223381). Our assembler tests did not cover serveral
different syntax variants. This patch expands the test coverage to check for
the following cases:

1. Modified immediate operands may be expressed with expressions, as in #(4 * 2)
instead of #8.

2. Modified immediate operands may be _optionally_ prefixed by a '#' symbol or a
'$' symbol.

3. Certain instructions (e.g. ADD) support single input register variants;
[ADD r0, #mod_imm] is same as [ADD r0, r0, #mod_imm].

4. Certain instructions have aliases which convert plain immediates to modified
immediates. For an example, [ADD r0, -10] is not valid because -10 (in two's
complement) cannot be encoded as a modified immediate, but ARMInstrInfo.td
defines an alias which can transform this into a [SUB r0, 10].

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223475 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 16:33:56 +00:00
Rafael Espindola
dd6794f01d Small cleanup on how we clear constant variables. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223474 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 16:05:19 +00:00
Chad Rosier
58f462fe5c Update TargetTriple format info.
Phabricator revision: http://reviews.llvm.org/D6543

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223473 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 16:05:14 +00:00
Chad Rosier
f69cd1de67 Fix typos in llvm/IR/Module.h
Phabricator revision: http://reviews.llvm.org/D6535

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223472 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 16:02:06 +00:00
Rafael Espindola
46cbde27ce Use an early return. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223470 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 15:42:30 +00:00
Evgeniy Stepanov
c4c08aab64 [msan] Avoid extra origin address realignment.
Do not realign origin address if the corresponding application
address is at least 4-byte-aligned.

Saves 2.5% code size in track-origins mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223464 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 14:34:03 +00:00
Andrea Di Biagio
54529ed1c4 [X86] Avoid introducing extra shuffles when lowering packed vector shifts.
When lowering a vector shift node, the backend checks if the shift count is a
shuffle with a splat mask. If so, then it introduces an extra dag node to
extract the splat value from the shuffle. The splat value is then used
to generate a shift count of a target specific shift.

However, if we know that the shift count is a splat shuffle, we can use the
splat index 'I' to extract the I-th element from the first shuffle operand.
The advantage is that the splat shuffle may become dead since we no longer
use it.

Example:

;;
define <4 x i32> @example(<4 x i32> %a, <4 x i32> %b) {
  %c = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer
  %shl = shl <4 x i32> %a, %c
  ret <4 x i32> %shl
}
;;

Before this patch, llc generated the following code (-mattr=+avx):
  vpshufd $0, %xmm1, %xmm1   # xmm1 = xmm1[0,0,0,0]
  vpxor  %xmm2, %xmm2
  vpblendw $3, %xmm1, %xmm2, %xmm1 # xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
  vpslld %xmm1, %xmm0, %xmm0
  retq

With this patch, the redundant splat operation is removed from the code.
  vpxor  %xmm2, %xmm2
  vpblendw $3, %xmm1, %xmm2, %xmm1 # xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
  vpslld %xmm1, %xmm0, %xmm0
  retq


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223461 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 12:13:30 +00:00
Charlie Turner
1610d6e878 Add missing FP build attribute tests.
The test file test/CodeGen/ARM/build-attributes.ll was missing several
floating-point build attribute tests. The intention of this commit is that for
each CPU / architecture currently tested, there are now tests that make sure
the following attributes are sufficiently checked,

  * Tag_ABI_FP_rounding
  * Tag_ABI_FP_denormal
  * Tag_ABI_FP_exceptions
  * Tag_ABI_FP_user_exceptions
  * Tag_ABI_FP_number_model

Also in this commit, the -unsafe-fp-math flag has been augmented with the full
suite of flags Clang sends to LLVM when you pass -ffast-math to Clang. That is,
`-unsafe-fp-math' has been changed to `-enable-unsafe-fp-math -disable-fp-elim
-enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast'

Change-Id: I35d766076bcbbf09021021c0a534bf8bf9a32dfc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223454 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 08:22:47 +00:00
Hal Finkel
138d5bf371 Revert "r223440 - Consider subregs when calling MI::registerDefIsDead for phys deps"
Reverting this because, while it fixes the problem in the reduced test case, it
does not fix the problem in the full test case from the bug report.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223442 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 02:07:35 +00:00
Hal Finkel
d281f1443a Consider subregs when calling MI::registerDefIsDead for phys deps
The scheduling dependency graph is built bottom-up within each scheduling
region, and ScheduleDAGInstrs::addPhysRegDeps is called to add output/anti
dependencies, based on physical registers, to the SUs for instructions
based on those that come before them.

In the test case, we start before post-RA scheduling with a block that looks
like this:

...
	INLINEASM <...
andc $0,$0,$2
stdcx. $0,0,$3
bne- 1b
> [sideeffect] [mayload] [maystore] [attdialect], $0:[regdef-ec:G8RC], %X6<earlyclobber,def,dead>, $1:[mem], %X3<kill>, $2:[reguse:G8RC], %X5<kill>, $3:[reguse:G8RC], %X3, $4:[mem], %X3, $5:[clobber], %CC<earlyclobber,imp-def,dead>, <<badref>>
	...
	%X4<def,dead> = ANDIo8 %X4<kill>, 1, %CR0<imp-def,dead>, %CR0GT<imp-def>
	...
	%R29<def> = ISEL %R3<undef>, %R4<kill>, %CR0GT<kill>

where it is relevant that %CC is an alias to %CR0, and that %CR0GT is a
subregister of %CR0. However, for post-RA scheduling, no dependency was added
to prevent the INLINEASM from being scheduled in between the ANDIo8 and the
ISEL (which communicate via the %CR0GT register).

In ScheduleDAGInstrs::addPhysRegDeps, when called for the %CC operand, we'd
iterate over all of its aliases (which include %CC itself and also %CR0), and
look for previously-encountered defs of those registers. We'd find the ANDIo8,
but decide not to add a dependency between the INLINEASM and the ANDIo8 because
both the INLINEASM's def of %CC is dead, and also the ANDIo8 def of %CR0 is
dead. This ignores, however, that ANDIo8 has a non-dead def of %CR0GT, a
subregister of %CR0, and thus a dependency still must exist.

To fix this problem, when calling registerDefIsDead on the SU with the def, we
also check all subregisters for possible non-dead defs, and add the dependency
if any are found.

Fixes PR21742.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223440 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 01:57:22 +00:00
Duncan P. N. Exon Smith
afcbfb40fb ADT: Remove GetStringMapEntryFromValue()
It relies on undefined behaviour, since `StringMapEntry<>` is not
a standard layout type.  There are no users anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223439 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 01:41:36 +00:00
Duncan P. N. Exon Smith
397b575f81 IR: Stop relying on GetStringMapEntryFromValue()
It relies on undefined behaviour.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223438 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 01:41:34 +00:00
Adrian Prantl
74fb019dd0 Cleanup: Calls to getDwarfRegNum() may actually fail, if there is
no DWARF register number mapping, or if the register was a virtual
register that was never materialized. Previously, we would just emit a
bogus location, after this patch we don't emit a location at all by
doing an early exit.

After my bugfix in r223401 today, this doesn't actually happen on any
target that I tested this with, but it's still preferable to make the
possibility of a failure explicit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223428 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 01:02:46 +00:00
Adrian Prantl
af25a5d9b7 Add a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223427 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 01:02:36 +00:00
Paul Robinson
ebde7405a7 Make GetSVN.cmake do its VCS queries with native CMake code.
This lets the queries work on Windows as well as Linux.

This does mean make and cmake aren't using the same scripts to do the
queries (again), but at least GetSVN.cmake understands git and git-svn
as well as svn now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223425 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 00:50:15 +00:00
Rafael Espindola
7eaee304ab linkGlobalVariableProto never returns null. Simplify the caller. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223424 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 00:30:47 +00:00
Eric Christopher
52978c2adf Rename the x86 isTargetMacho to isTargetMachO for uniformity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223421 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 00:22:38 +00:00
Eric Christopher
62b1007007 Both of these subtargets have functions that check whether or
not the target is mach-o. Use them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223420 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 00:22:35 +00:00
Rafael Espindola
aa8cddcd3a Move merging of alignment to a central location. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223418 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-05 00:09:02 +00:00