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150 Commits

Author SHA1 Message Date
Craig Topper
4c763ee613 Add AVX2 variable shift instructions and intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143915 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 08:26:24 +00:00
Craig Topper
28692044db Add AVX2 VPMOVMASK instructions and intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143904 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 03:20:35 +00:00
Craig Topper
69f5df7778 Add AVX2 VEXTRACTI128 and VINSERTI128 instructions. Fix VPERM2I128 to be qualified with HasAVX2 instead of HasAVX. Mark VINSERTF128 and VEXTRACTF128 as never having side effects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143902 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 02:00:04 +00:00
Craig Topper
9595ede514 Fix accidental edit to __builtin_ia32_vperm2f128_ps256's name 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143901 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 00:54:28 +00:00
Craig Topper
c8eb880a7f More AVX2 instructions and their intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-06 23:04:08 +00:00
Craig Topper
27e5d0c72a Add more AVX2 instructions and intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143861 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-06 06:12:20 +00:00
Craig Topper
018262768f Add intrinsics for X86 vcvtps2ph and vcvtph2ps instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143683 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 06:59:49 +00:00
Craig Topper
98e0b9c86d Add new X86 AVX2 VBROADCAST instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143612 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 07:35:53 +00:00
Craig Topper
205e3378fd More AVX2 instructions and intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143536 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 06:54:17 +00:00
Craig Topper
3f2b2c218f Add a bunch more X86 AVX2 instructions and their corresponding intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143529 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 04:42:13 +00:00
Craig Topper
ce7de9f36d Fix operand type for x86 pmadd_ub_sw intrinsic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143455 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-01 07:25:22 +00:00
Craig Topper
782c8fbd6e Fix operand type for int_x86_ssse3_phadd_sw_128 intrinsic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143336 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 07:16:37 +00:00
Craig Topper
6b1c5fc02a Begin adding AVX2 instructions. No selection support yet other than intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143331 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-31 02:15:10 +00:00
Craig Topper
e7b05504fa Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143319 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-30 19:57:21 +00:00
Craig Topper
26ec44f7cf Mark X86 pcmpeq b/w/d intrinsics as being Commutative. pcmpeqq is already marked as Commutative. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143317 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-30 18:33:35 +00:00
Craig Topper
6762427e8e Fix return type for X86 mpsadbw instrinsic. The instruction takes in a vector of 8-bit integers, but produces a vector of 16-bit integers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143313 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-30 17:22:45 +00:00
Craig Topper
b4c945716f Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142642 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 06:55:01 +00:00
Craig Topper
717cdb0df8 Rename PEXTR to PEXT. Add intrinsics for BMI instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-19 07:48:35 +00:00
Chad Rosier
62660310d9 Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. 
crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and
crc64.[8|16|32] have been renamed to .crc32.64.[8|64].




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132163 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-26 23:13:19 +00:00
Bill Wendling
fffb61d042 Remove dead intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130831 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 02:40:54 +00:00
Michael J. Spencer
4babeeeeed Add 3DNow! intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129551 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 00:32:41 +00:00
Michael J. Spencer
9a0bac41b3 Fix whitespace and tabs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-14 14:33:36 +00:00
Bill Wendling
f93f7b2446 Reapply r129401 with patch for clang. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129419 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 00:36:11 +00:00
Bill Wendling
f9b2dc66c8 Revert r129401 for now. Clang is using the old way of doing things. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129403 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 22:59:27 +00:00
Bill Wendling
d5f323d70b Remove the unaligned load intrinsics in favor of using native unaligned loads. 
Now that we have a first-class way to represent unaligned loads, the unaligned
load intrinsics are superfluous.

First part of <rdar://problem/8460511>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129401 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 22:46:31 +00:00
Bill Wendling
6cf6c79e82 The pshufw instruction came about in MMX2 when SSE was introduced. Don't place 
it in with the SSSE3 instructions.

Steward! Could you place this chair by the aft sun deck? I'm trying to get away
from the Astors. They are such boors!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115552 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-04 20:24:01 +00:00
Chris Lattner
591d76ea5a the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115473 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 19:09:13 +00:00
Dale Johannesen
0488fb649a Massive rewrite of MMX: 
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.

Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics. 

MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces.  Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.

The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 23:57:10 +00:00
Dale Johannesen
86097c384f Add patterns for MMX that use the new intrinsics. 
Enable palignr intrinsic.
These may need adjustment for a new VT in due course.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113233 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 18:10:56 +00:00
Bill Wendling
74f9cb2cac Revert int_x86_mmx_palignr_b intrinsic to match llvm-gcc's version. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112886 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 22:31:53 +00:00
Bill Wendling
bc54ee9a77 - Change __builtin_ia32_palignr intrinsic type to match the pattern in clang. 
- Add patterns to match the following MMX builtins:

   * __builtin_ia32_vec_init_v8qi
   * __builtin_ia32_vec_init_v4hi
   * __builtin_ia32_vec_init_v2si
   * __builtin_ia32_vec_ext_v2si

  These builtins do not correspond to a single MMX instruction. They will have
  to be lowered -- most likely in the back-end.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112881 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 22:26:35 +00:00
Dale Johannesen
97511ceffa Recommit with changes. Comment out palignr for the 
moment, as there's a testcase that uses it and expects it
to be subject to optimizations; we won't be doing that.
Some adjustments based on feedback from Bill.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112754 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-01 22:43:48 +00:00
Dale Johannesen
6e3665bcd0 Revert 112740, it broke some clang tests somehow... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112744 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-01 21:36:44 +00:00
Dale Johannesen
6a94cbb72e Add a few more missing MMX operations. This should be it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112740 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-01 21:03:03 +00:00
Dale Johannesen
c88d829c87 Add some MMX intrinsics that duplicate functionality 
available in normal llvm operators.  We aren't going to
use those for MMX any more because it's unsafe for the
optimizers to synthesize new MMX instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-01 00:40:09 +00:00
Chris Lattner
d80c7e1232 Add a new llvm.x86.int intrinsic, allowing access to the 
x86 int and int3 instructions.  Patch by Peter Housel!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111831 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 19:39:25 +00:00
Bruno Cardoso Lopes
ec1355b17b Remove rsqrt/sqrt_nr intrinsics since there are no more builtins for them on clang 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110845 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 19:21:05 +00:00
Bruno Cardoso Lopes
1a76359347 Remove AVX 256-bit cast intrinsics now that clang is using __builtin_shufflevector for those 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110772 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 02:15:33 +00:00
Bruno Cardoso Lopes
9fb2ffd568 Remove AVX 256-bit unpack and interleave intrinsics now that clang is using __builtin_shufflevector for those 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110769 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 01:44:11 +00:00
Bruno Cardoso Lopes
b89c631b77 Remove AVX 256-bit shuffle intrinsics now that clang is using __builtin_shufflevector for those 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110767 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 01:18:26 +00:00
Bruno Cardoso Lopes
0115387005 Remove replicate intrinsics, clang will generate shufflevector for those. The shuffles can't be matched by x86 codegen yet, but will soon 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110647 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 02:25:35 +00:00
Bruno Cardoso Lopes
77497bf196 Use i32 instead of i8 for dot product intrinsic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110643 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 01:40:05 +00:00
Bruno Cardoso Lopes
d5955f5a23 Fix the last argument type of AVX vblend intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110628 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 00:00:22 +00:00
Bruno Cardoso Lopes
4945dd8314 Patterns to match AVX 256-bit vzero intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110480 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-06 22:10:01 +00:00
Bruno Cardoso Lopes
f6d6df4006 Remove unused AVX intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110407 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-06 00:04:07 +00:00
Dan Gohman
7365c091f9 Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMem 
to IntrReadWriteArgMem, as it's for reading as well as writing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110395 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 23:36:21 +00:00
Bruno Cardoso Lopes
12cf5018be Fix a comment typo and add more 256-bit intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-04 01:09:40 +00:00
Bruno Cardoso Lopes
e5c500b37d Support x86 AVX 256-bit instruction intrinsics. Right now support all of them, but 
as soon as we properly codegen the simple vector operations in clang, remove the
unnecessary builti-ins/intrinsics from clang and llvm.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110094 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-03 01:53:41 +00:00
Eric Christopher
7e2f5aaa67 Make sure aeskeygenassist uses an unsigned immediate field. 
Fixes rdar://8017638


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104617 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 17:33:22 +00:00
Eric Christopher
6d972fd087 Remove the palignr intrinsics now that we lower them to vector shuffles, 
shifts and null vectors. Autoupgrade these to what we'd lower them to.

Add a testcase to exercise this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101851 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 00:59:54 +00:00