We now insert accumulator variables as necessary to eliminate tail recursion
more aggressively. This is still fairly limited, but allows us to transform
fib/factorial, and other functions into nice happy loops. :)
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The only functionality change is that we now implement:
Regression/Transforms/TailCallElim/intervening-inst.ll
Which is really kinda pointless, because it means that trivially dead code
does not interfere with -tce, but trivially dead code probably wouldn't be
around anytime when this pass is run anyway.
The point of including this change it to support other more aggressive
transformations when we have the analysis capabilities to do so.
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which never worked itself. The cee pass still doesn't work, but it doesn't use
this method anymore anyway, so eliminate the method.
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on the algorithm for directly computing immediate dominators presented in this
paper:
A Fast Algorithm for Finding Dominators in a Flowgraph
T. Lengauer & R. Tarjan, ACM TOPLAS July 1979, pgs 121-141.
This _substantially_ speeds up construction of all dominator related information.
Post-dominators to follow.
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each basic block in function. Instead, just emit a stream of instructions,
chopping up basic blocks based on when we find terminator instructions. This
saves a fairly substantial chunk of bytecode space. In stripped, sample
cases, for example, we get this reduction in size:
197.parser: 163036 -> 137180: 18.8% reduction
254.gap : 844936 -> 689392: 22.6%
255.vortex: 621724 -> 528444: 17.7%
...
Not bad for something this simple. :) Note that this doesn't require a new
bytecode version number at all, though version 1.1 should not need to support
the old format.
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Eventually this pass will provide substantially better code in the interim between when we
have a crappy isel and nice isel. Unfortunately doing so requires fixing the backend to
actually SUPPORT all of the fancy addressing modes that we now generate, and writing a DCE
pass for machine code. Each of these is a fairly substantial job, so this will remain disabled
for the immediate future. :(
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folding of instructions into addressing modes. This creates lots of dead
instructions, which are currently not deleted. It also creates a lot of
instructions that the X86 backend currently cannot handle. :(
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bug where spill instructions were added to the next basic block
instead of the end of the current one if the instruction that required
the spill was the last in the block.
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allow unaligned loads, that is probably the problem I've been seeing in numerous
SPARC test cases failing. X86, on the other hand, just slows down unaligned
accesses, since it must make 2 aligned accesses for each unaligned one.
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* Finegrainify namespacification of Linker.cpp
* If linking a library in fails, do not STOP LINKING IN LIBRARIES AND
CONTINUE ANYWAY! Instead, just output the warning, and keep going. :)
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