Commit Graph

36 Commits

Author SHA1 Message Date
Evan Cheng
f46e7e3d7f Remove RegClass2VRegMap from MachineRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133967 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 23:54:40 +00:00
Jakob Stoklund Olesen
f462e3fac7 Make it possible to have unallocatable register classes.
Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.

TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.

The goal here is to eliminate use cases for overriding allocation_order_*
methods.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02 23:07:20 +00:00
Devang Patel
68e6beeccc Revert r124611 - "Keep track of incoming argument's location while emitting LiveIns."
In other words, do not keep track of argument's location.  The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body.
This requires some coordination with debugger to get this working. 
 - The debugger needs to be aware of prolog_end attribute attached with line table entries.
 - The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126155 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-21 23:21:26 +00:00
Devang Patel
e9a7ea6865 Keep track of incoming argument's location while emitting LiveIns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124611 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-31 21:38:14 +00:00
Jakob Stoklund Olesen
994c727b57 Use IndexedMap for MachineRegisterInfo as well. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-09 03:05:46 +00:00
Jakob Stoklund Olesen
bf4699c561 Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.
This function is intended to be used when inserting a machine instruction that
trivially restricts the legal registers, like LEA requiring a GR32_NOSP
argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 23:54:39 +00:00
Jakob Stoklund Olesen
1e1098c6f3 Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108062 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 22:42:59 +00:00
Dan Gohman
fe5e4dabbf Teach EmitLiveInCopies to omit copies for unused virtual registers,
and to clean up unused incoming physregs from the live-in list.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106805 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 22:23:02 +00:00
Dan Gohman
71f095b20a Don't leak RegClass2VRegMap, which is now a new[] array instead of a
std::vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106298 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 18:54:05 +00:00
Dan Gohman
a606d955de Start TargetRegisterClass indices at 0 instead of 1, so that
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 18:13:55 +00:00
Benjamin Kramer
0f9c658558 Remove unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105100 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-29 14:03:51 +00:00
Evan Cheng
701d4d309f Remove schedule-livein-copies. It's not being used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105095 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-29 02:23:39 +00:00
Evan Cheng
3946043a80 Avoid adding duplicate function live-in's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104560 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 21:33:37 +00:00
Dan Gohman
49b4589978 Add a utility function for conservatively clearing kill flags, and make
use of it in MachineCSE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 19:24:00 +00:00
Jakob Stoklund Olesen
8e8b3cb937 Silence warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 20:51:04 +00:00
Jakob Stoklund Olesen
82b07dc499 Simplify the tracking of used physregs to a bulk bitor followed by a transitive
closure after allocating all blocks.

Add a few more test cases for -regalloc=fast.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103500 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 20:30:28 +00:00
Dan Gohman
34dcc6fadc Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:33:48 +00:00
Evan Cheng
2ad0fcf794 Replace r102368 with code that's less fragile. This creates DBG_VALUE instructions for function arguments early and insert them after instruction selection is done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102554 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 23:08:54 +00:00
Evan Cheng
f48023b3cf Insert dbg_value instructions for function entry block liveins (i.e. function arguments).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102368 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 19:16:00 +00:00
Dan Gohman
b13033f61c Move the code for initialing the entry block livein set out of
SelectionDAGISel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101258 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 17:05:00 +00:00
Dan Gohman
98708260f5 Move the code for emitting livein copies out of SelectionDAGISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101254 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 16:51:49 +00:00
Dan Gohman
13e73f483e Move MachineRegisterInfo's isLiveIn and isLiveOut out of line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101145 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 16:55:37 +00:00
Evan Cheng
1423c70b8f Add MachineRegisterInfo::hasOneUse and hasOneNonDBGUse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97663 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 21:18:38 +00:00
Dan Gohman
2bf0649e05 Simplify a few more uses of reg_iterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82812 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 22:26:13 +00:00
Evan Cheng
358dec5180 Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 08:28:29 +00:00
Evan Cheng
90f95f88c6 Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73346 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-14 20:22:55 +00:00
Dan Gohman
33f1c68cba Move MachineRegisterInfo::setRegClass out of line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69126 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15 01:19:35 +00:00
Dan Gohman
2e3e5bf427 Move createVirtualRegister out-of-line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60684 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-08 04:54:11 +00:00
Evan Cheng
11a26f3697 Add a register class -> virtual registers map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57844 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-20 20:03:28 +00:00
Dan Gohman
03bafaf802 Assert that all MachineInstrs update PhysRegUseDefLists in
their cleanup code. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53194 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-07 19:55:35 +00:00
Evan Cheng
1eb5cf9c7d Added debugging routine dumpUses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47042 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13 02:45:38 +00:00
Dan Gohman
6f0d024a53 Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-10 18:45:23 +00:00
Chris Lattner
e138b3dd1f switch the register iterator to act more like hte LLVM value iterator: dereferencing
it now returns the machineinstr of the use.  To get the operand, use I.getOperand().

Add a new MachineRegisterInfo::replaceRegWith, which is basically like
Value::replaceAllUsesWith.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45482 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01 20:36:19 +00:00
Chris Lattner
a91a7d594f Add a trivial but handy function to efficiently return the machine
instruction that defines the specified vreg.  Crazy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45480 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01 03:07:29 +00:00
Chris Lattner
62ed6b9ade Implement automatically updated def/use lists for all MachineInstr register
operands.  The lists are currently kept in MachineRegisterInfo, but it does
not yet provide an iterator interface to them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45477 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01 01:12:31 +00:00
Chris Lattner
84bc5427d6 Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled.  Given this expanded name, we can start 
moving other stuff into it.  For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-31 04:13:23 +00:00