Elena Demikhovsky
a6269ee5fb
AVX-512: fixed shuffle lowering
...
in case of BLEND and added VSHUFPS patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192055 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 06:11:18 +00:00
Venkatraman Govindaraju
20b10abf4e
[Sparc] Custom lower addc/adde/subc/sube on i64 in sparc64.
...
This is required because i64 is a legal type but addxcc/subxcc reads icc carry bit, which are 32 bit conditional codes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192054 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 03:36:18 +00:00
Venkatraman Govindaraju
bb0ec9840b
[Sparc] Use addxcc/subxcc for adde/sube instead of addx/subx.
...
addx/subx does not modify conditional codes whereas addxcc/subxx does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192053 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 02:11:10 +00:00
Benjamin Kramer
87855d3013
Emit a better error when running out of registers on inline asm.
...
The most likely case where this error happens is when the user specifies
too many register operands. Don't make it look like an internal LLVM bug
when we can see that the error is coming from an inline asm instruction.
For other instructions we keep the "ran out of registers" error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192041 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 19:33:37 +00:00
Craig Topper
22abf7e17f
Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns are sufficient.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192039 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 19:22:59 +00:00
Craig Topper
e2522fd06c
Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into (sub -2, x).
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192037 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 17:17:53 +00:00
Jiangning Liu
beb6afa843
Implement aarch64 neon instruction set AdvSIMD (Across).
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192028 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 08:22:10 +00:00
Rafael Espindola
e8bcb9dd99
Convert test to FileCheck.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192025 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 02:58:36 +00:00
Venkatraman Govindaraju
a8147756d6
[Sparc] Use correct alignment while loading/storing fp128 values.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192023 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 02:29:47 +00:00
Venkatraman Govindaraju
b648122c5f
[Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP with fp128 operand.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192015 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 00:31:41 +00:00
Venkatraman Govindaraju
1c9524b624
[Sparc] Correct the floating point conditional code mapping in GetOppositeBranchCondition().
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 23:54:30 +00:00
Reed Kotler
5404ed811d
Support tblockaddr for static compilation in Mips16.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 22:01:40 +00:00
Akira Hatanaka
60ccc3b0ec
[mips] Fix a bug in MipsLongBranch::replaceBranch, which was erasing
...
instructions in delay slots along with the original branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191978 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 20:51:40 +00:00
Matthias Braun
d1bd8d904c
ARM: optimizeSelect has to consider the previous register class
...
optimizeSelect folds (predicated) copy instructions, it must not ignore
the original register class of the operand when replacing the register
with the copies dest register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191963 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 16:52:56 +00:00
Matthias Braun
4e54f41d6c
ARM: do not add a regmask for TAILJUMPs
...
The jump doesn't really kill the registers, the following call does but
we never get back anyway.
This avoids some verify-machineinstrs problems when TAILJUMPs are
if-converted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191962 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 16:52:54 +00:00
Matthias Braun
e1bde51d63
ARM: preserve undef flag in pseudo instruction expanders
...
Copy over the whole register machine operand instead of creating a new one
with an incomplete set of flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191961 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 16:52:51 +00:00
Jiangning Liu
dd518bcc9d
Implement aarch64 neon instruction set AdvSIMD (3V elem).
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191944 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 09:20:44 +00:00
Logan Chien
20357662a0
[arm] Enhance the test case by checking .fpu directive.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191891 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-03 12:18:56 +00:00
Craig Topper
dfd1014ec3
Remove duplicated test cases that occurred when I applied the same patch file to my model twice.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191873 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-03 04:27:14 +00:00
Craig Topper
fafe4bbd6c
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191871 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-03 04:16:45 +00:00
Elena Demikhovsky
c699417f11
AVX-512: fixed a bug in getLoadStoreRegOpcode() for AVX-512 target
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191818 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-02 12:20:42 +00:00
Vincent Lejeune
dfef7cbfc6
R600: add a pass that merges clauses.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191790 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 19:32:58 +00:00
Vincent Lejeune
c6c37d74a2
R600: Put PRED_X instruction in its own clause
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191789 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 19:32:49 +00:00
Vincent Lejeune
5b00e833fa
R600: Enable -verify-machineinstrs in some tests.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191788 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 19:32:38 +00:00
Preston Gurd
8df451fc0b
Add test case for PR16785.
...
Thanks for Dimitry Andric, Rafael Espindola, and Benjamin Kramer
for providing and progressively reducing the test case!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191782 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 17:02:48 +00:00
Richard Sandiford
e22c56d6d8
[SystemZ] Add comparisons of high words and memory
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191777 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 15:00:44 +00:00
Richard Sandiford
185ef05ad6
[SystemZ] Add comparisons of large immediates using high words
...
There are no corresponding patterns for small immediates because they would
prevent the use of fused compare-and-branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191775 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 14:56:23 +00:00
Richard Sandiford
ad366a3f67
[SystemZ] Add immediate addition involving high words
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 14:53:46 +00:00
Richard Sandiford
bd1958d8e9
[SystemZ] Extend test-under-mask support to high GR32s
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191773 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 14:41:52 +00:00
Richard Sandiford
f985f01574
[SystemZ] Extend 32-bit RISBG optimizations to high words
...
This involves using RISB[LH]G, whereas the equivalent z10 optimization
uses RISBG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191770 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 14:36:20 +00:00
Richard Sandiford
00f5335ea0
[SystemZ] Extend pseudo conditional 8- and 16-bit stores to high words
...
As the comment says, we always want to use STOC for 32-bit stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191767 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 14:33:55 +00:00
Tim Northover
bba9390fc6
ARM: support interrupt attribute
...
This function-attribute modifies the callee-saved register list and function
epilogue (specifically the return instruction) so that a routine is suitable
for use as an interrupt-handler of the specified type without disrupting
user-mode applications.
rdar://problem/14207019
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191766 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 14:33:28 +00:00
Richard Sandiford
6d2158acae
[SystemZ] Add test missing from r191764.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191765 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 14:31:50 +00:00
Richard Sandiford
b9dcca8265
[SystemZ] Allow integer AND involving high words
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191762 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 14:20:41 +00:00
Richard Sandiford
1ff62e182e
[SystemZ] Allow integer XOR involving high words
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191759 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 14:08:44 +00:00
Richard Sandiford
1c831f7f1f
[SystemZ] Allow integer OR involving high words
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191755 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 13:22:41 +00:00
Richard Sandiford
645d250b84
[SystemZ] Allow integer insertions with a high-word destination
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191753 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 13:18:56 +00:00
Richard Sandiford
4708657097
[SystemZ] Allow selects with a high-word destination
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191751 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 13:10:16 +00:00
Richard Sandiford
4c8feae136
[SystemZ] Add patterns to load a constant into a high word (IIHF)
...
Similar to low words, we can use the shorter LLIHL and LLIHH if it turns
out that the other half of the GR64 isn't live.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191750 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 13:02:28 +00:00
Richard Sandiford
79e2ed4d83
[SystemZ] Add register zero extensions involving at least one high word
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191746 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 12:49:07 +00:00
Joey Gouly
d1311ac171
[ARM] Introduce the 'sevl' instruction in ARMv8.
...
This also removes the restriction on the immediate field of the 'hint'
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191744 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 12:39:11 +00:00
Richard Sandiford
9813dbf396
[SystemZ] Add truncating high-word stores (STCH and STHH)
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191743 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 12:22:49 +00:00
Richard Sandiford
9a05f040e7
[SystemZ] Add zero-extending high-word loads (LLCH and LLHH)
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191742 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 12:19:08 +00:00
Richard Sandiford
ced450f0e6
[SystemZ] Add sign-extending high-word loads (LBH and LHH)
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191740 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 12:11:47 +00:00
Richard Sandiford
55d7d83b6c
[SystemZ] Use upper words of GR64s for codegen
...
This just adds the basics necessary for allocating the upper words to
virtual registers (move, load and store). The move support is parameterised
in a way that makes it easy to handle zero extensions, but the associated
zero-extend patterns are added by a later patch.
The easiest way of testing this seemed to be add a new "h" register
constraint for high words. I don't expect the constraint to be useful
in real inline asms, but it should work, so I didn't try to hide it
behind an option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191739 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 11:26:28 +00:00
Daniel Sanders
7f768e0368
[mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics)
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191737 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 10:22:35 +00:00
Elena Demikhovsky
c8d0d00781
AVX-512: Added X86vzmovl patterns
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191733 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 08:38:02 +00:00
Manman Ren
e267f04ef5
TBAA: update tbaa format from scalar format to struct-path aware format.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191690 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 18:17:55 +00:00
Manman Ren
aef1b37824
TBAA: remove !tbaa from testing cases when they are not needed.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191689 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 18:17:35 +00:00
Robert Wilhelm
f80a63fa23
Fix spelling intruction -> instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191610 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-28 11:46:15 +00:00