Commit Graph

27 Commits

Author SHA1 Message Date
Brian Gaeke
90c5bbe100 Add M_TERMINATOR_FLAG to terminator instructions (branches and returns).
Also, the RETURN instructions are not used in the sparcv9 backend.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14559 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-02 04:57:37 +00:00
Brian Gaeke
3ca4fccac5 Fix file header comments and include guards -- many files have been moved or
renamed since they were last spiffed up, or they just never had proper comments
in the first place.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13148 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-25 07:04:49 +00:00
Tanya Lattner
f048bfd97d fix bug in previous checkin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12044 91177308-0d34-0410-b5e6-96231b3b80d8
2004-03-01 15:05:17 +00:00
Chris Lattner
0755912c38 Remove a TON of flags that noone cares about
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11983 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-29 05:58:30 +00:00
John Criswell
856ba76200 Added LLVM copyright header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9321 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-21 15:17:13 +00:00
Vikram S. Adve
ddafa49edc RDCCR defines arg. #1, not arg. #2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6796 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-20 11:32:11 +00:00
Chris Lattner
c8621e6f28 These instructions really take three operands. This fixes some assertions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6765 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-18 15:09:02 +00:00
Misha Brukman
d36e30e623 * Changed Bcc instructions to behave like BPcc instructions
* BPA and BPN do not take a %cc register as a parameter
* SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions
* Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit
* Added WRCCR{r,i} opcodes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6655 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-06 09:52:23 +00:00
Misha Brukman
e085a9d279 Added MOVR (move int reg on register condition), aka comparison with zero.
None of these instructions are actually used in the Sparc backend, so no changes
were required in the instruction selector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6549 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-02 21:16:54 +00:00
Misha Brukman
eecdb661ec SparcInstr.def: added 'r' and 'i' versions of MOV(F)cc instructions
SparcInstrSelection.cpp:
* Fixed opcodes to return correct 'i' version since the two functions are each
  only used in one place.
* Changed name of function to have an 'i' in the name to signify that they each
  return an immediate form of the opcode.
* Added a warning if either of the functions is ever used in a context which
  requires a register-version opcode.

SparcV9_F4.td: fixed class F4_3, added F4_4 and notes that F4_{1,2} need fixing
SparcV9.td: added the MOV(F)cc instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6548 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-02 20:55:14 +00:00
Misha Brukman
ed36fd8da6 Made the register and immediate versions of instructions consecutive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6439 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 19:14:01 +00:00
Misha Brukman
6ddd9d87a7 One of the first major changes to make the work of JITting easier: adding
annotations on instructions to specify which format they are (i.e., do they take
2 registers and 1 immediate or just 3 registers) as that changes their binary
representation and hence, code emission.

This makes instructions more like how X86 defines them to be. Now, writers of
instruction selection must choose the correct opcode based on what instruction
type they are building, which they already know. Thus, the JIT doesn't have to
do the same work by `discovering' which operands an instruction really has.

As this involves lots of small changes to a lot of files in lib/target/Sparc,
I'll commit them individually because otherwise the diffs will be unreadable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6371 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:32:38 +00:00
Chris Lattner
3501feab81 Rename MachineInstrInfo -> TargetInstrInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5272 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-14 22:00:31 +00:00
Chris Lattner
9a8e4121aa Remove all traces of the "Opcode Mask" field in the MachineInstr class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4359 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-28 21:17:20 +00:00
Chris Lattner
232c3be0b5 Fix misspelling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4276 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-25 01:43:26 +00:00
Vikram S. Adve
e0048667dd Don't mark JMPLCALL and JMPLRET as branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4132 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-13 00:22:32 +00:00
Vikram S. Adve
ac67006bed Return address register should be marked as "result" for the JMPL instruction
since it is defined by the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3966 91177308-0d34-0410-b5e6-96231b3b80d8
2002-09-28 17:00:15 +00:00
Vikram S. Adve
97da3649dd BA has only one argument.
Added LDFSR, LDXFSR, STFSR and STXFSR.
Fixed operands info for RDCCR, WRCCR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2835 91177308-0d34-0410-b5e6-96231b3b80d8
2002-07-08 23:25:17 +00:00
Vikram S. Adve
585612e556 Change latencies for Load, Store and Branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1965 91177308-0d34-0410-b5e6-96231b3b80d8
2002-03-24 03:33:53 +00:00
Vikram S. Adve
c9c6aa0445 Change latency of SETX to improve schedule -- just a hack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1304 91177308-0d34-0410-b5e6-96231b3b80d8
2001-11-14 15:54:44 +00:00
Ruchira Sasanka
d63aaaaabe Added M_PSEUDO_FLAG for SETX .. instr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1301 91177308-0d34-0410-b5e6-96231b3b80d8
2001-11-14 15:35:13 +00:00
Vikram S. Adve
b7f06f46a1 Fixed instruction information for RDCCR and WRCCR.
Fixed selection to create a TmpInstruction for each integer CC register
(since it is an implicit side-effect, unlike FP CC registers which are
explicit operands).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1120 91177308-0d34-0410-b5e6-96231b3b80d8
2001-11-04 19:34:49 +00:00
Ruchira Sasanka
3839e6e309 Added code to support correct saving of %ccr across calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1111 91177308-0d34-0410-b5e6-96231b3b80d8
2001-11-03 19:59:59 +00:00
Vikram S. Adve
c7b2e5c81e Add SETX instruction for 64-bit constants.
Add M_CC_FLAG for many instructions that use int or fp CC registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1006 91177308-0d34-0410-b5e6-96231b3b80d8
2001-10-28 21:41:01 +00:00
Vikram S. Adve
1d86cc06dc Added SAVE and RESTORE. Duplicated JMPL into JMPLCALL and JMPLRET,
which have the same opcode and operands but different flags.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@938 91177308-0d34-0410-b5e6-96231b3b80d8
2001-10-22 13:32:55 +00:00
Vikram S. Adve
6e64ef4008 Change latency of setuw and setsw to 2 cycles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@681 91177308-0d34-0410-b5e6-96231b3b80d8
2001-09-30 23:46:57 +00:00
Chris Lattner
9a3d63bcbe Seperate instruction definitions into new SparcInstr.def file
Move contents of SparcMachineInstrDesc[] out of SparcInternals.h
into Sparc.cpp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@644 91177308-0d34-0410-b5e6-96231b3b80d8
2001-09-19 15:56:23 +00:00