Commit Graph

124 Commits

Author SHA1 Message Date
Benjamin Kramer
a4f0aad951 [C++11] Replace llvm::tie with std::tie.
The old implementation is no longer needed in C++11.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202644 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 13:30:33 +00:00
Alp Toker
18510b7e43 [C++11] Expand and eliminate the LLVM_ENUM_INT_TYPE() macro
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202607 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 03:20:38 +00:00
Reid Kleckner
73f615b0bd Explicitly request unsigned enum types when desired
This fixes repeated -Wmicrosoft warnings when self-hosting clang on
Windows, and gets us real unsigned enum types with MSVC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192227 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08 20:15:11 +00:00
Benjamin Kramer
87855d3013 Emit a better error when running out of registers on inline asm.
The most likely case where this error happens is when the user specifies
too many register operands. Don't make it look like an internal LLVM bug
when we can see that the error is coming from an inline asm instruction.
For other instructions we keep the "ran out of registers" error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192041 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 19:33:37 +00:00
Adrian Prantl
818833f279 Debug info: Fix PR16736 and rdar://problem/14990587.
A DBG_VALUE is register-indirect iff the first operand is a register
_and_ the second operand is an immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190821 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-16 23:29:03 +00:00
Craig Topper
a0ec3f9b7b Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-14 04:42:23 +00:00
Adrian Prantl
43ae5e85f8 Use the appropriate unsigned int type for the offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186015 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-10 16:56:52 +00:00
Adrian Prantl
3517640443 Reapply an improved version of r180816/180817.
Change the informal convention of DBG_VALUE machine instructions so that
we can express a register-indirect address with an offset of 0.
The old convention was that a DBG_VALUE is a register-indirect value if
the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE
is register-indirect if the first operand is a register and the second
operand is an immediate. For plain register values the combination reg,
reg is used. MachineInstrBuilder::BuildMI knows how to build the new
DBG_VALUES.

rdar://problem/13658587

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185966 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-09 20:28:37 +00:00
David Blaikie
6d9dbd5526 Debug Info: Simplify Frame Index handling in DBG_VALUE Machine Instructions
Rather than using the full power of target-specific addressing modes in
DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This
reduces the complexity of debug info handling down to two
representations of values (reg+offset and frame index+offset) rather
than three or four.

Ideally we could ensure that frame indicies had been eliminated by the
time we reached an assembly or dwarf generation, but I haven't spent the
time to figure out where the FIs are leaking through into that & whether
there's a good place to convert them. Some FI+offset=>reg+offset
conversion is done (see PrologEpilogInserter, for example) which is
necessary for some SelectionDAG assumptions about registers, I believe,
but it might be possible to make this a more thorough conversion &
ensure there are no remaining FIs no matter how instruction selection
is performed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184066 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-16 20:34:15 +00:00
Jakob Stoklund Olesen
601158a18e Make RAFast::UsedInInstr indexed by register units.
This fixes some problems with too conservative checking where we were
marking all aliases of a register as used, and then also checking all
aliases when allocating a register.

<rdar://problem/13249625>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175782 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21 19:35:21 +00:00
Jakob Stoklund Olesen
b45e4deb10 Remove special-casing of return blocks for liveness.
Now that return value registers are return instruction uses, there is no
need for special treatment of return blocks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174416 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 18:21:52 +00:00
Chandler Carruth
0b8c9a80f2 Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 11:36:10 +00:00
Jakob Stoklund Olesen
7b79b9862c Use MachineInstrBuilder in a few CodeGen passes.
This automatically passes a context pointer to MI->addOperand().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170711 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 18:08:06 +00:00
Chandler Carruth
d04a8d4b33 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03 16:50:05 +00:00
Jakob Stoklund Olesen
39b5c0c049 Use MCPhysReg for RegisterClassInfo allocation orders.
This saves a bit of memory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168852 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29 03:34:17 +00:00
Chad Rosier
18bb0545ff Revert r168630, r168631, and r168633 as these are causing nightly test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168751 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-28 00:21:29 +00:00
Chad Rosier
728aede2e9 Now that the X86 Maximal Stack Alignment Check pass has been removed (i.e.,
r168627), we no longer need to call the freezeReservedRegs() function a second
time.  Previously, this pass was conservatively adding the FP to the set of
reserved registers, requiring the second update to the reserved registers.
rdar://12719844

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168631 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-26 23:25:41 +00:00
Chad Rosier
7979b24e5c [regallocfast] Make sure the MachineRegisterInfo is aware of clobbers from a
register masks.  This is an obvious and necessary fix for a soon to be committed
patch.  No test case possible at this time.  Reviewed by Jakob.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167498 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06 22:52:42 +00:00
Akira Hatanaka
bab24216cc Change signature of function RAFast::spillAll to avoid conversion between
type MachineInstr* and MachineBasicBlock::iterator.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167088 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31 00:56:01 +00:00
Jakob Stoklund Olesen
d7ea7d5cd7 Use a SparseSet instead of a BitVector for UsedInInstr in RAFast.
This is just as fast, and it makes it possible to avoid leaking the
UsedPhysRegs BitVector implementation through
MachineRegisterInfo::addPhysRegsUsed().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166083 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-17 01:37:59 +00:00
Jakob Stoklund Olesen
14d1dd95c7 Remove RegisterClassInfo::isReserved() and isAllocatable().
Clients can use the equivalent functions in MRI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165990 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 22:41:03 +00:00
David Blaikie
986d76d7b3 Tidy up a few more uses of MF.getFunction()->getName().
Based on CR feedback from r162301 and Craig Topper's refactoring in r162347
here are a few other places that could use the same API (& in one instance drop
a Function.h dependency).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162367 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22 17:18:53 +00:00
Jakob Stoklund Olesen
4e6966266a Don't use getNextOperandForReg() in RAFast.
That particular optimization was probably premature anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161541 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08 23:44:01 +00:00
Andrew Trick
1525260b3e Move RegisterClassInfo.h.
Allow targets to access this API. It's required for RegisterPressure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158102 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06 20:29:31 +00:00
Jakob Stoklund Olesen
396618b43a Switch all register list clients to the new MC*Iterator interface.
No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157854 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01 23:28:30 +00:00
Jakob Stoklund Olesen
8c70ea47fa Simplify some more getAliasSet callers.
MCRegAliasIterator can include Reg itself in the list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157848 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01 22:38:17 +00:00
Jakob Stoklund Olesen
6565a70970 Don't access MO reference after invalidating operand list.
This should unbreak llvm-x86_64-linux.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156778 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14 21:30:58 +00:00
Jakob Stoklund Olesen
4d10829e12 Fix PR12821.
RAFast must add an <imp-def> operand when it is rewriting a sub-register
def that isn't a read-modify-write.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156777 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14 21:10:25 +00:00
Andrew Trick
c0ccb8bb17 SparseSet: Add support for key-derived indexes and arbitrary key types.
This nicely handles the most common case of virtual register sets, but
also handles anticipated cases where we will map pointers to IDs.

The goal is not to develop a completely generic SparseSet
template. Instead we want to handle the expected uses within llvm
without any template antics in the client code. I'm adding a bit of
template nastiness here, and some assumption about expected usage in
order to make the client code very clean.

The expected common uses cases I'm designing for:
- integer keys that need to be reindexed, and may map to additional
  data
- densely numbered objects where we want pointer keys because no
  number->object map exists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155227 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 20:05:28 +00:00
Craig Topper
fac2598149 Use uint16_t to store instruction implicit uses and defs. Reduces static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08 08:22:45 +00:00
Craig Topper
e4fd907e72 Use uint16_t to store register overlaps to reduce static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04 10:43:23 +00:00
Jakob Stoklund Olesen
91ba63d230 80 col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151167 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22 16:50:46 +00:00
Jakob Stoklund Olesen
a240743ad9 Use SparseSet for the RAFast live virtual register map.
This makes RAFast 4% faster, and it gets rid of the dodgy DenseMap
iteration.

This also revealed that RAFast would sometimes dereference DenseMap
iterators after erasing other elements from the map. That does seem to
work in the current DenseMap implementation, but SparseSet doesn't allow
it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151111 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22 01:02:37 +00:00
Andrew Trick
19273aec44 Clear virtual registers after they are no longer referenced.
Passes after RegAlloc should be able to rely on MRI->getNumVirtRegs() == 0.
This makes sharing code for pre/postRA passes more robust.
Now, to check if a pass is running before the RA pipeline begins, use MRI->isSSA().
To check if a pass is running after the RA pipeline ends, use !MRI->getNumVirtRegs().

PEI resets virtual regs when it's done scavenging.

PTX will either have to provide its own PEI pass or assign physregs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151032 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-21 04:51:23 +00:00
Jakob Stoklund Olesen
d9f0ff56a1 Transfer regmasks to MRI.
MRI keeps track of which physregs have been used. Make sure it gets
updated with all the regmask-clobbered registers.

Delete the closePhysRegsUsed() function which isn't necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150830 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17 19:07:56 +00:00
Andrew Trick
8dd26253f5 RegAlloc superpass: includes phi elimination, coalescing, and scheduling.
Creates a configurable regalloc pipeline.

Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa.

When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>.

CodeGen transformation passes are never "required" as an analysis

ProcessImplicitDefs does not require LiveVariables.

We have a plan to massively simplify some of the early passes within the regalloc superpass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10 04:10:36 +00:00
Andrew Trick
ab78e20ce0 Obvious unnecessary loop removal. Follow through from previous checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149398 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31 18:54:19 +00:00
Andrew Trick
b3d58474c8 RAFast: Generalize the logic for return operands.
This removes implicit assumption about the form of MI coming into regalloc. In particular, it should be independent of ProcessImplicitDefs which will eventually become a standard part of coming out of SSA--unless we simply can eliminate IMPLICIT_DEF completely. Current unit tests expose this once I remove incidental pass ordering restrictions.

This is not a final fix. Just a temporary workaround until I figure out the right way.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149360 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31 05:55:32 +00:00
Jakob Stoklund Olesen
d9e5c764bf Freeze reserved registers before starting register allocation.
The register allocators don't currently support adding reserved
registers while they are running.  Extend the MRI API to keep track of
the set of reserved registers when register allocation started.

Target hooks like hasFP() and needsStackRealignment() can look at this
set to avoid reserving more registers during register allocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147577 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05 00:26:49 +00:00
Evan Cheng
5a96b3dad2 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 07:15:52 +00:00
Rafael Espindola
254a13282c If a register is both an early clobber and part of a tied use, handle the use
before the clobber so that we copy the value if needed.

Fixes pr11415.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145056 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-22 06:27:18 +00:00
Devang Patel
d2df64f569 Insert modified DBG_VALUE into LiveDbgValueMap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 21:03:58 +00:00
Jakob Stoklund Olesen
9d812a2805 Better diagnostics when inline asm fails to allocate.
asm.c:2:7: error: ran out of registers during register allocation
  asm(""::"r"(0), "r"(1), "r"(2), "r"(3), "r"(4), "r"(5), "r"(6), "r"(7), "r"(8), "r"(9));
        ^

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134310 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 07:17:37 +00:00
Evan Cheng
e837dead3c - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 19:10:37 +00:00
Jakob Stoklund Olesen
27ce3b96e5 Print registers by name instead of by number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134013 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 17:24:32 +00:00
Devang Patel
6f373a87cb After register is spilled there should not be any DBG_VALUE referring the same register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21 23:02:36 +00:00
Devang Patel
72d9b0e4fc There could be more than one DBG_VALUE instructions for variables where all of them have offset based on one register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21 22:36:03 +00:00
Jakob Stoklund Olesen
5e5ed44577 Be less aggressive about hinting in RAFast.
In particular, don't spill dirty registers only to satisfy a hint. It is
not worth it.

The attached test case provides an example where the fast allocator
would spill a register when other registers are available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-13 03:26:46 +00:00
Jakob Stoklund Olesen
448ab3ab39 Avoid calling TRI->getAllocatableSet in RAFast.
When compiling a program with lots of small functions like
483.xalancbmk, this makes RAFast 11% faster.

Add some comments to clarify the difference between unallocatable and
reserved registers. It's quite subtle.

The fast register allocator depends on EFLAGS' not being allocatable on
x86. That way it can completely avoid tracking liveness, and it won't
mind when there are multiple uses of a single def.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132514 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02 23:41:40 +00:00
Jakob Stoklund Olesen
5d20c3152b Use RegisterClassInfo::getOrder in RAFast.
This saves two virtual function calls and an Allocatable BitVector test,
making RAFast run 2% faster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132471 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02 18:35:30 +00:00