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Author SHA1 Message Date
Chad Rosier
aa645f78a2 Simplify logic. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163648 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 20:57:04 +00:00
Chad Rosier
a7b159ccdd [ms-inline asm] Split the parsing of IR asm strings into GCC and MS variants. 
Add support in the EmitMSInlineAsmStr() function for handling integer consts.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163645 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 19:09:56 +00:00
Manman Ren
020aba0c3b SimplifyCFG: preserve branch-weight metadata when creating a new switch from 
a pair of switch/branch where both depend on the value of the same variable and
the default case of the first switch/branch goes to the second switch/branch.

Code clean up and fixed a few issues:
1> handling the case where some cases of the 2nd switch are invalidated
2> correctly calculate the weight for the 2nd switch when it is a conditional eq

Testing case is modified from Alastair's original patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163635 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 17:43:35 +00:00
Jakob Stoklund Olesen
a6035773d8 Add TRI::getSubRegIndexLaneMask(). 
Sub-register lane masks are bitmasks that can be used to determine if
two sub-registers of a virtual register will overlap. For example, ARM's
ssub0 and ssub1 sub-register indices don't overlap each other, but both
overlap dsub0 and qsub0.

The lane masks will be accurate on most targets, but on targets that use
sub-register indexes in an irregular way, the masks may conservatively
report that two sub-register indices overlap when the eventually
allocated physregs don't.

Irregular register banks also mean that the bits in a lane mask can't be
mapped onto register units, but the concept is similar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163630 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 16:34:08 +00:00
Jakob Stoklund Olesen
de0250728b Clean the sub-reg index composition maps at emission. 
Preserve the Composites map in the CodeGenSubRegIndex class so it can be
used to determine which sub-register indices can actually be composed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163629 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 16:34:05 +00:00
Jakob Stoklund Olesen
59f45e4610 Add MCRI::getNumSubRegIndices() and start checking SubRegIndex ranges. 
Apparently, NumSubRegIndices was completely unused before. Adjust it by
one to include the null subreg index, just like getNumRegs() includes
the null register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163628 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 16:34:02 +00:00
Chad Rosier
ef68cfa8b8 Formatting. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163627 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 16:33:10 +00:00
Nadav Rotem
1eba4a7a28 Dragonegg selfhost exposed additional cases where alloca usage moved outside of lifetime markers. Disabling the pass for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163623 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 15:40:27 +00:00
Nadav Rotem
50bdea299c Enable stack coloring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163617 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 13:48:35 +00:00
Nadav Rotem
8754bbbe67 Stack Coloring: Dont crash on dbg values which use stack frames. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163616 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 12:34:27 +00:00
Evgeniy Stepanov
468a95fb04 CMake toolchain file for Android NDK. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163612 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 11:54:27 +00:00
Duncan Sands
25a4fcce67 Add IRC handle. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163601 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 07:50:40 +00:00
Craig Topper
55b2405484 Make a bunch of lowering helper functions static instead of member functions. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163596 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 06:15:32 +00:00
Craig Topper
9e6dc8b9e7 Change unsigned to a uint16_t in static disassembler tables to reduce the table size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163594 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 04:19:21 +00:00
NAKAMURA Takumi
0dd9b61f9f llvm/lib/Transforms/Utils/CMakeLists.txt: Update. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163593 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 02:55:37 +00:00
Alex Rosenberg
95f1ef4ac7 Add a pass that renames everything with metasyntatic names. This works well after using bugpoint to reduce the confusion presented by the original names, which no longer mean what they used to. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163592 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 02:46:18 +00:00
Craig Topper
dd201ff1dc Teach DAG combiner to constant fold FABS of a BUILD_VECTOR of ConstantFPs. Factor similar code out of FNEG DAG combiner. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163587 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 01:45:21 +00:00
Chandler Carruth
7b617158db Add support for finding cacheflush on OpenBSD/mips64 platforms. 
Patch by Brad Smith!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163584 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 01:17:24 +00:00
Andrew Trick
78e5efe1b2 Reorganize MachineScheduler interfaces and publish them in the header. 
The Hexagon target decided to use a lot of functionality from the
target-independent scheduler. That's fine, and other targets should be
able to do the same. This reorg and API update makes that easy.

For the record, ScheduleDAGMI was not meant to be subclassed. Instead,
new scheduling algorithms should be able to implement
MachineSchedStrategy and be done. But if need be, it's nice to be
able to extend ScheduleDAGMI, so I also made that easier. The target
scheduler is somewhat more apt to break that way though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163580 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 00:39:15 +00:00
Andrew Trick
88df977d4a Remove unused declaration 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163579 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 00:39:12 +00:00
Eric Christopher
09e4750919 Revert r160148 it seems to cause more problems than it should 
right now. We'll fix PR13303 a different way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163570 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 23:34:06 +00:00
Eric Christopher
4984e01fd5 80-col fixup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163569 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 23:34:03 +00:00
Eric Christopher
edf8bc8c88 80-col fixup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163568 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 23:34:00 +00:00
Eric Christopher
5c38de99f1 No reason to construct this twice. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163567 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 23:33:57 +00:00
Chad Rosier
2cfe90b119 Add newline. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163565 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 23:09:27 +00:00
Chad Rosier
35c688932a Update function names to conform to guidelines. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163561 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 22:50:57 +00:00
Chad Rosier
1dc2591e9e Revert r163556. Missed updates to tablegen files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163557 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 22:30:35 +00:00
Chad Rosier
16c5584548 Update function names to conform to guidelines. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163556 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 22:23:45 +00:00
NAKAMURA Takumi
985dcfc351 test/CodeGen/X86/ms-inline-asm.ll: Relax for non-darwin x86 targets. '##InlineAsm' could not be seen in other hosts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163554 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 22:04:54 +00:00
Chad Rosier
24f5fddbdf [ms-inline asm] Properly emit the asm directives when the AsmPrinterVariant 
and InlineAsmVariant don't match.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163550 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 21:36:05 +00:00
Chad Rosier
5c3dcb7bc0 Update test case for Release builds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163549 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 21:31:43 +00:00
Dmitri Gribenko
2de0572cae Remove redundant semicolons which are null statements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163547 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 21:26:47 +00:00
Nadav Rotem
8631a90f46 Disable stack coloring because it makes dragonegg fail bootstrapping. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163545 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 21:17:58 +00:00
Chad Rosier
3b132fab0b [ms-inline asm] Pass the correct AsmVariant to the PrintAsmOperand() function 
and update the printOperand() function accordingly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163544 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 21:10:49 +00:00
Chad Rosier
3c4ecd7dab [ms-inline asm] Add support for .att_syntax directive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163542 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 20:54:39 +00:00
Nadav Rotem
b6d52a5b4a Enable stack coloring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163539 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 20:15:49 +00:00
Jakob Stoklund Olesen
519daf5d2d Don't attempt to use flags from predicated instructions. 
The ARM backend can eliminate cmp instructions by reusing flags from a
nearby sub instruction with similar arguments.

Don't do that if the sub is predicated - the flags are not written
unconditionally.

<rdar://problem/12263428>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163535 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 19:17:25 +00:00
Michael J. Spencer
2c38a6615a [Object] Extract Elf_Ehdr. Patch by Hemant Kulkarni! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163532 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 19:04:02 +00:00
Nadav Rotem
6165dba25f Stack Coloring: Handle the case where END markers come before BEGIN markers properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163530 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 18:51:09 +00:00
Michael Liao
b8150d8523 Enhance PR11334 fix to support extload from v2f32/v4f32 
- Fix an remaining issue of PR11674 as well



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163528 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 18:33:51 +00:00
Sergei Larin
7ae51be2a3 Add "blocked" heuristic to the Hexagon MI scheduler. 
Improve AQ instruction selection in the Hexagon MI scheduler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163523 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 17:31:34 +00:00
Michael Ilseman
10def396cb Fold multiply by 0 or 1 when in UnsafeFPMath mode in SelectionDAG::getNode(). 
This folding happens as early as possible for performance reasons, and to make sure it isn't foiled by other transforms (e.g. forming FMAs).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163519 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 17:00:37 +00:00
Michael Ilseman
06b9690463 whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163518 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 16:56:31 +00:00
Michael Liao
7fdc66bf73 Add boolean simplification support from CMOV 
- If a boolean value is generated from CMOV and tested as boolean value,
  simplify the use of test result by referencing the original condition.
  RDRAND intrinisc is one of such cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163516 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 16:36:16 +00:00
James Molloy
8cd08bf4ac Fix an assertion failure when optimising a shufflevector incorrectly into concat_vectors, and a followup bug with SelectionDAG::getNode() creating nodes with invalid types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163511 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 14:01:21 +00:00
Nadav Rotem
ff1b63172d Minor cleanup. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163510 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 13:20:00 +00:00
Nadav Rotem
9438d1e351 Stack Coloring: Debug prints to print the slot number and not the array index. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163509 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 13:17:58 +00:00
Nadav Rotem
a7de8a61df Stack Coloring: When searching for disjoint regions, do not compare intervals twice or to theirself. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163508 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 12:47:38 +00:00
Nadav Rotem
e47feeb823 Stack Coloring: Add support for multiple regions of the same slot, within a single basic block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163507 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 12:39:35 +00:00
Elena Demikhovsky
8100d244ff The VPSHUFB 256-bit instruction may be generated when one of input vector is undefined or zeroinitializer. 
I've added the "zeroinitializer" case in this patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163506 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 12:13:11 +00:00