Owen Anderson
43967a97cf
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135290 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-15 18:46:47 +00:00
Johnny Chen
de29a52940
The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions
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(single element or n-element structure to all lanes).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129550 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 00:10:45 +00:00
Johnny Chen
3cf3059b11
Add a VEXT test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 22:04:01 +00:00
Johnny Chen
8424a60fc9
The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values
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for USAD8 and USADA8.
rdar://problem/9247060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 01:05:52 +00:00
Johnny Chen
4d81c9a6ba
A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"
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Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.
rdar://problem/9239922
rdar://problem/9239596
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 20:49:02 +00:00
Johnny Chen
a9611549fe
Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.
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Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.
rdar://problem/9240648
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 18:27:46 +00:00
Johnny Chen
c3281c10c9
A7.3 register encoding
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Qd -> bit[12] == 0
Qn -> bit[16] == 0
Qm -> bit[0] == 0
If one of these bits is 1, the instruction is UNDEFINED.
rdar://problem/9238399
rdar://problem/9238445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 22:57:07 +00:00
Johnny Chen
2d66cec9dd
Fix incorrect alignment for NEON VST2b32_UPD.
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rdar://problem/9225433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128841 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 20:35:31 +00:00
Johnny Chen
c39b6271be
Handle the added VBICiv*i* NEON instructions, too.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128243 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 22:04:39 +00:00
Johnny Chen
b4ac342ea0
The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the
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VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 18:40:38 +00:00
Johnny Chen
83cf2ffdcd
Add one more test case for VFP Load/Store Multiple (vpop).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 20:21:08 +00:00
Dale Johannesen
2ae2302abc
Segregate tests by target.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 18:14:32 +00:00
