Commit Graph

403 Commits

Author SHA1 Message Date
Evan Cheng
0521928ae7 Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpy
etc. takes an option OptSize. If OptSize is true, it would return
the inline limit for functions with attribute OptSize.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122952 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-06 06:52:41 +00:00
Evan Cheng
3d2125c9db Enable sibling call optimization of libcalls which are expanded during
legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120501 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 23:55:39 +00:00
Chris Lattner
de189be53f add TLI support indicating that jumps are more expensive than logical operations
and use this to disable a specific optimization.  Patch by Micah Villmow!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30 18:12:52 +00:00
Benjamin Kramer
f788854d20 Prune includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118342 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 11:45:59 +00:00
Duncan Sands
cdfad36b40 Simplify uses of MVT and EVT. An MVT can be compared directly
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118169 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 12:17:33 +00:00
John Thompson
47245422a4 Mult-alt constraint incremental development step 3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:37:38 +00:00
John Thompson
44ab89eb37 Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 17:29:13 +00:00
Dale Johannesen
e93d99cf07 Remove Synthesizable from the Type system; as MMX vector
types are no longer Legal on X86, we don't need it.
No functional change.  8499854.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116947 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 21:32:10 +00:00
John Thompson
eac6e1d0c7 Added skeleton for inline asm multiple alternative constraint support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113766 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-13 18:15:37 +00:00
Chris Lattner
cd11e9db35 add a specialization for the MVT form of getTypeAction, since it is
trivial.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112105 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25 23:05:45 +00:00
Chris Lattner
aafe626c7f remove some llvmcontext arguments that are now dead post-refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25 23:00:45 +00:00
Chris Lattner
e6f7c267df Change handling of illegal vector types to widen when possible instead of
expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats.  This
affects two places in the code: handling cross block values and handling
function return and arguments.  Since vectors are already widened by 
legalizetypes, this gives us much better code and unblocks x86-64 abi
and SPU abi work.

For example, this (which is a silly example of a cross-block value):
define <4 x float> @test2(<4 x float> %A) nounwind {
 %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>
 %C = fadd <2 x float> %B, %B
  br label %BB
BB:
 %D = fadd <2 x float> %C, %C
 %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ret <4 x float> %E
}

Now compiles into:

_test2:                                 ## @test2
## BB#0:
 addps %xmm0, %xmm0
 addps %xmm0, %xmm0
 ret

previously it compiled into:

_test2:                                 ## @test2
## BB#0:
 addps %xmm0, %xmm0
 pshufd $1, %xmm0, %xmm1
                                        ## kill: XMM0<def> XMM0<kill> XMM0<def>
 insertps $0, %xmm0, %xmm0
 insertps $16, %xmm1, %xmm0
 addps %xmm0, %xmm0
 ret

This implements rdar://8230384



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112101 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25 22:49:25 +00:00
Anton Korobeynikov
cec36f4c11 Hook in GlobalMerge pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109359 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-24 21:52:08 +00:00
Evan Cheng
3144687df7 - Allow target to specify when is register pressure "too high". In most cases,
it's too late to start backing off aggressive latency scheduling when most
  of the registers are in use so the threshold should be a bit tighter.
- Correctly handle live out's and extract_subreg etc.
- Enable register pressure aware scheduling by default for hybrid scheduler.
  For ARM, this is almost always a win on # of instructions. It's runtime
  neutral for most of the tests. But for some kernels with high register
  pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by
  54 and sped up by 20%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 22:39:59 +00:00
Evan Cheng
4f6b4674be Teach bottom up pre-ra scheduler to track register pressure. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 06:09:07 +00:00
Evan Cheng
d70f57b254 ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 22:15:08 +00:00
Evan Cheng
46dcb57e18 Teach computeRegisterProperties() to compute "representative" register class for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64.
This property will be used by the register pressure tracking instruction scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 18:47:01 +00:00
Rafael Espindola
9d544d0416 Fix a typo and fit in 80 columns. Found by Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108164 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 18:11:17 +00:00
Rafael Espindola
cbeeae23c3 Fix va_arg for doubles. With this patch VAARG nodes always contain the
correct alignment information, which simplifies ExpandRes_VAARG a bit.

The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:

* The 's' in target data: If this is set to the minimal alignment of any
  argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
  example.
* The getTransientStackAlignment method. It is possible for an architecture to
  have argument less aligned than what we maintain the stack pointer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 04:01:49 +00:00
Dan Gohman
84023e0fbe Reapply bottom-up fast-isel, with several fixes for x86-32:
- Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 09:00:22 +00:00
Bob Wilson
02266e29f9 --- Reverse-merging r107947 into '.':
U    utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U    test/CodeGen/X86/fast-isel.ll
U    test/CodeGen/X86/fast-isel-loads.ll
U    include/llvm/Target/TargetLowering.h
U    include/llvm/Support/PassNameParser.h
U    include/llvm/CodeGen/FunctionLoweringInfo.h
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/CodeGen/FastISel.h
U    include/llvm/CodeGen/SelectionDAGISel.h
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/CallingConvLower.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U    lib/CodeGen/SelectionDAG/FastISel.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.h
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86ISelLowering.h


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 16:37:18 +00:00
Dan Gohman
bf87e24917 Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:39:23 +00:00
Dan Gohman
f595141525 Revert 107840 107839 107813 107804 107800 107797 107791.
Debug info intrinsics win for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 01:00:56 +00:00
Dan Gohman
f423a69839 Add X86FastISel support for return statements. This entails refactoring
a bunch of stuff, to allow the target-independent calling convention
logic to be employed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107800 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 18:32:53 +00:00
Dan Gohman
a4160c3434 Simplify FastISel's constructor by giving it a FunctionLoweringInfo
instance, rather than pointers to all of FunctionLoweringInfo's
members.

This eliminates an NDEBUG ABI sensitivity.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107789 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 16:29:44 +00:00
Dan Gohman
c9403659a9 Split the SDValue out of OutputArg so that SelectionDAG-independent
code can do calling-convention queries. This obviates OutputArgReg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 15:54:55 +00:00
Dan Gohman
ce5172098d Move ArgFlagsTy, OutputArg, and InputArg out of SelectionDAGNodes.h and
into a new header, TargetCallingConv.h.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107782 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 15:28:42 +00:00
Dan Gohman
c9af33c685 CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.
SelectBasicBlock doesn't needs its BasicBlock argument.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107712 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 22:19:37 +00:00
Eric Christopher
f7a0c7bf8b Fix up -fstack-protector on linux to use the segment
registers.  Split out testcases per architecture and os
now.

Patch from Nelson Elhage.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 05:18:56 +00:00
Evan Cheng
13151432ed Change if-conversion block size limit checks to add some flexibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 22:42:03 +00:00
Dale Johannesen
1784d160e4 The hasMemory argument is irrelevant to how the argument
for an "i" constraint should get lowered; PR 6309.  While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 21:55:36 +00:00
Dan Gohman
4e39e9da0f Reapply r106634, now that the bug it exposed is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 14:30:44 +00:00
Daniel Dunbar
cbe762b5d1 Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 17:09:26 +00:00
Jim Grosbach
9a526495e0 Some targets don't require the fencing MEMBARRIER instructions surrounding
atomic intrinsics, either because the use locking instructions for the
atomics, or because they perform the locking directly. Add support in the
DAG combiner to fold away the fences.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106630 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 16:07:42 +00:00
Jim Grosbach
b9cd499dec remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106628 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 15:49:18 +00:00
Dan Gohman
8a7f7426ee Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,
which is faster, simpler, and less surprising.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106263 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 01:05:21 +00:00
Evan Cheng
1cc3984148 Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 23:26:43 +00:00
Evan Cheng
211ffa1351 Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:19:50 +00:00
Evan Cheng
06b666c705 Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 02:18:07 +00:00
Evan Cheng
0ebf356ddf Get rid of the bit twiddling to read / set OpActions and ValueTypeActions. The small saving in memory isn't worth the increase in runtime and code complexity in my opinion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103768 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 07:37:40 +00:00
Evan Cheng
b9c0e332b3 Eliminate use of magic numbers to access OpActions. It also has the effect of allowing more than 31 scalar value types. MAX_ALLOWED_VALUETYPE had already been updated to 64 a while back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103743 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 23:25:21 +00:00
Evan Cheng
b21f5a5511 Fix up LoadExtActions, TruncStoreActions, and IndexedModeActions representation and setter and getter's so they will continue to work if the number of scalar ValueType's exceeds 31.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103742 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 23:01:26 +00:00
Evan Cheng
1e5a6c46b8 80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103733 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 20:14:58 +00:00
Dan Gohman
038df88e28 Trim #includes and forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103489 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 19:11:43 +00:00
Dan Gohman
ff7a562751 Implement a bunch more TargetSelectionDAGInfo infrastructure.
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 17:31:57 +00:00
Dan Gohman
419e4f9263 Remove the TargetLowering::getSubtarget() virtual function, which
was unused. TargetMachine::getSubtarget() is used instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103474 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 16:21:03 +00:00
Dan Gohman
af1d8ca44a Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01 00:01:06 +00:00
Evan Cheng
962021bc7f - Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 07:38:55 +00:00
Dale Johannesen
f822e733af Stop abusing EmitInstrWithCustomInserter for target-dependent
form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets.  Add a new hook instead.
No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102320 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-25 21:33:54 +00:00
Dan Gohman
f81eca0ab9 Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel
and into SelectionDAGBuilder and FastISel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102123 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-22 20:46:50 +00:00