Commit Graph

61208 Commits

Author SHA1 Message Date
Nick Lewycky
ae9f07e0b8 Fix a bug in codegenprep where it was losing track of values OptimizeMemoryInst
by switching to a ValueMap. Patch by Andrea DiBiagio!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181397 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08 09:00:10 +00:00
David Majnemer
363160a6be DAGCombiner: Simplify inverted bit tests
Fold (xor (and x, y), y) -> (and (not x), y)

This removes an opportunity for a constant to appear twice.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181395 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08 06:44:42 +00:00
David Blaikie
aa76a93cd3 Debug Info: Support DW_TAG_imported_declaration
This provides basic functionality for imported declarations. For
subprograms and types some amount of lazy construction is supported (so
the definition of a function can proceed the using declaration), but it
still doesn't handle declared-but-not-defined functions (since we don't
generally emit function declarations).

Variable support is really rudimentary at the moment - simply looking up
the existing definition with no support for out of order (declaration,
imported_module, then definition).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181392 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08 06:01:41 +00:00
David Blaikie
d1221e377d Finish renaming constructImportedModuleDIE to constructImportedEntityDIE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181391 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08 06:01:38 +00:00
Eric Christopher
9c57ad2381 Pass the MDNode in and do the insertion at compile unit creation time
instead of relying upon an extra call to finish initializing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181383 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08 00:58:51 +00:00
Eric Christopher
1db3d0820f Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181378 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08 00:11:10 +00:00
Arnold Schwaighofer
280e1df858 LoopVectorizer: Improve reduction variable identification
The two nested loops were confusing and also conservative in identifying
reduction variables. This patch replaces them by a worklist based approach.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181369 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 21:55:37 +00:00
Kevin Enderby
88535dda90 Fix a bug in the MC asm parser evaluating expressions. It was treating:
A = 9
B = 3 * A - 2 * A + 1 as  B = 3 * A - (2 * A + 1)

rdar://13816516


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 21:40:58 +00:00
David Blaikie
20d9e41ddb Rename DIImportedModule to DIImportedEntity and allow imported declarations
DIBuilder::createImportedDeclaration isn't fully plumbed through (note,
lacking in AsmPrinter/DwarfDebug support) but this seemed like a
sufficiently useful division of code to make the subsequent patch(es)
easier to follow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181364 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 21:35:53 +00:00
Charles Davis
8cb6b97160 MCStreamer: Also clear vector of W64UnwindInfos on reset().
Patch by Kai Nacke!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181363 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 21:14:15 +00:00
Bob Wilson
32ec93d431 Remove redundant check and use cached FrameArray values.
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181355 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 20:56:33 +00:00
Rafael Espindola
e449654815 Remove exception handling support from the old JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181354 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 20:53:59 +00:00
Matt Arsenault
798925bac7 Fix vselect when getSetCCResultType returns a different type from the operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181348 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 20:24:18 +00:00
Preston Gurd
acccd2edc8 Corrected Atom latencies for SSE SQRT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181346 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 19:57:34 +00:00
Jyotsna Verma
f931f691ee Hexagon: Fix Small Data support to handle -G 0 correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181344 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 19:53:00 +00:00
David Blaikie
498c91e341 Debug Info: Fix for break due to r181271
Apparently we didn't keep an association of Compile Unit metadata nodes
to DIEs so looking up that parental context failed & thus caused no
DW_TAG_imported_modules to be emitted at the CU scope. Fix this by
adding the mapping & sure up the test case to verify this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181339 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 17:57:13 +00:00
Hal Finkel
8a88cadaed Cleanup PPCInstrInfo::optimizeCompareInstr
Implement suggestions by Bill Schmidt in post-commit review. No functionality
change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181338 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 17:49:55 +00:00
Jyotsna Verma
ddcf3ee768 Reverting r181331.
Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181334 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 17:12:35 +00:00
Jyotsna Verma
81fda3b4d5 Hexagon: Fix Small Data support to handle -G 0 correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181331 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 16:42:15 +00:00
Jyotsna Verma
8cc93593cd Hexagon: Set accessSize and addrMode on all load/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181324 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 15:06:29 +00:00
Michael Kuperstein
c208c43a8a Re-enable AVX detection on x64 platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181313 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 14:05:33 +00:00
Richard Sandiford
7a1ead46fb [SystemZ] Fix InitMCCodeGenInfo call
createSystemZMCCodeGenInfo was not passing the optimization level to
InitMCCodeGenInfo(), so -O0 would be ignored.  Fixes DebugInfo/namespace.ll
after the changes in r181271.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181312 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 12:56:31 +00:00
Timur Iskhodzhanov
664fbee9c8 Fix the VS2010 build broken by r181271
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181296 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 07:47:47 +00:00
Arnold Schwaighofer
eb95cec176 LoopVectorize: getConsecutiveVector must respect signed arithmetic
We were passing an i32 to ConstantInt::get where an i64 was needed and we must
also pass the sign if we pass negatives numbers. The start index passed to
getConsecutiveVector must also be signed.

Should fix PR15882.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181286 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 04:37:05 +00:00
David Blaikie
d2e0f7ee15 DebugInfo: Support imported modules in lexical blocks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181271 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:33:07 +00:00
Tom Stellard
3d834a44f6 R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181269 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:02:19 +00:00
Tom Stellard
ea73bd8a54 R600/SI: Handle arbitrary destination type in SITargetLowering::adjustWritemask
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181268 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:02:15 +00:00
Tom Stellard
651a4c8ee0 R600/SI: Add intrinsic for texture image loading
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181267 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:02:12 +00:00
Tom Stellard
e756ffd888 R600/SI: Add pattern for uint_to_fp
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:02:07 +00:00
Tom Stellard
586862ae23 R600/SI: Add patterns for integer maxima / minima
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181265 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:02:04 +00:00
Tom Stellard
354769ba32 R600/SI: Add pattern for AMDGPU.trunc intrinsic
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181263 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 23:02:00 +00:00
Krzysztof Parzyszek
942940a326 Print IR from Hexagon MI passes with -print-before/after-all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181255 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:58:00 +00:00
Andrew Trick
61e0172197 Implemented public interface for modifying registered (not positional or sink options) command line options at runtime.
Patch by Dan Liew!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181254 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:56:35 +00:00
Andrew Trick
b7ad33b719 Support command line option categories.
Patch by Dan Liew!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181253 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:56:23 +00:00
Krzysztof Parzyszek
b072090f39 Cleanup of the HexagonTargetMachine setup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181250 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:25:45 +00:00
David Majnemer
8ec23cb07e InstCombine: (X ^ signbit) + C -> X + (signbit ^ C)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181249 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:21:31 +00:00
Eric Christopher
e305e03d6f Hoist boundary condition out of loop header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181248 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:19:44 +00:00
Eric Christopher
5a0c366b1f Untabify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181247 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:19:41 +00:00
Jyotsna Verma
1a7eab3878 Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 18:49:23 +00:00
Krzysztof Parzyszek
ed6fe299cf Make references to HexagonTargetMachine "const".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181233 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 18:38:37 +00:00
Andrew Trick
fcf79528da Rotate multi-exit loops even if the latch was simplified.
Test case by Michele Scandale!

Fixes PR10293: Load not hoisted out of loop with multiple exits.

There are few regressions with this patch, now tracked by
rdar:13817079, and a roughly equal number of improvements. The
regressions are almost certainly back luck because LoopRotate has very
little idea of whether rotation is profitable. Doing better requires a
more comprehensive solution.

This checkin is a quick fix that lacks generality (PR10293 has
a counter-example). But it trivially fixes the case in PR10293 without
interfering with other cases, and it does satify the criteria that
LoopRotate is a loop canonicalization pass that should avoid
heuristics and special cases.

I can think of two approaches that would probably be better in
the long run. Ultimately they may both make sense.

(1) LoopRotate should check that the current header would make a good
loop guard, and that the loop does not already has a sufficient
guard. The artifical SimplifiedLoopLatch check would be unnecessary,
and the design would be more general and canonical. Two difficulties:

- We need a strong guarantee that we won't endlessly rotate, so the
  analysis would need to be precise in order to avoid the
  SimplifiedLoopLatch precondition.

- Analysis like this are usually based on SCEV, which we don't want to
  rely on.

(2) Rotate on-demand in late loop passes. This could even be done by
shoving the loop back on the queue after the optimization that needs
it. This could work well when we find LICM opportunities in
multi-branch loops. This requires some work, and it doesn't really
solve the problem of SCEV wanting a loop guard before the analysis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:58:18 +00:00
Tom Stellard
32c76107d0 R600: Remove dead code from the CodeEmitter v2
v2:
  - Replace switch statement with TSFlags query

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:50:57 +00:00
Tom Stellard
f07b5373d7 R600: Emit config values in register / value pairs
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181228 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:50:51 +00:00
Eric Christopher
30cb836a20 Remove unnecessary instance variable and rework logic accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181227 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:50:50 +00:00
Eric Christopher
3bf2bcd96c Grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:50:46 +00:00
Tom Stellard
4f3d8a6440 R600: Stop emitting the instruction type byte before each instruction
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181225 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:50:44 +00:00
Eric Christopher
93f3fed999 Don't emit .dwo sections unless they exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181224 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:50:42 +00:00
Tom Stellard
58bf662c06 R600: Emit ISA for CALL_FS_* instructions
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:50:26 +00:00
Ulrich Weigand
e5c8c24ed5 [SystemZ] Update non-pic DWARF encodings
As pointed out by Rafael Espindola, we should match the DWARF encodings
produced by GCC in both pic and non-pic modes.  This was not the case
for the non-pic case.

This patch changes all DWARF encodings to DW_EH_PE_absptr for the
non-pic case, just like GCC does.  The test case is updated to check
for both variants.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181222 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:28:30 +00:00
Adhemerval Zanella
f51d7e76ae PowerPC: Fix unimplemented relocation on ppc64
This patch handles the R_PPC64_REL64 relocation type for powerpc64
for mcjit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 17:21:23 +00:00