Commit Graph

2501 Commits

Author SHA1 Message Date
Dan Gohman
afc36a9520 Previously, RecursivelyDeleteDeadInstructions provided an option
of returning a list of pointers to Values that are deleted. This was
unsafe, because the pointers in the list are, by nature of what
RecursivelyDeleteDeadInstructions does, always dangling. Replace this
with a simple callback mechanism. This may eventually be removed if
all clients can reasonably be expected to use CallbackVH.

Use this to factor out the dead-phi-cycle-elimination code from LSR
utility function, and generalize it to use the
RecursivelyDeleteTriviallyDeadInstructions utility function.

This makes LSR more aggressive about eliminating dead PHI cycles;
adjust tests to either be less trivial or to simply expect fewer
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70636 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-02 18:29:22 +00:00
Chris Lattner
c650f1f141 'The attached patch fixes an issue where llc -march=cpp fails with
"Invalid primitive type" on input containing the x86_fp80 type.'
Patch by Collin Winter!




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-01 23:54:26 +00:00
Evan Cheng
8c1474050d Mark MOV8mr_NOREX and MOV8rm_NOREX as mayStore / mayLoad respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70461 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-30 00:58:57 +00:00
Chris Lattner
6c147293d6 fix a regression handling indirect results: these need to be considered
memory operands otherwise the writebacks get lost when the inline asm 
doesn't otherwise have side effects.  This fixes rdar://6839427, though
clang really shouldn't generate these anymore.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70455 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-30 00:48:50 +00:00
Nate Begeman
ec8eee2d3a Fix infinite recursion in the C++ code which handles movddup by making it unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70425 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 22:47:44 +00:00
Evan Cheng
96f3fd9a7f spillPhysRegAroundRegDefsUses() may have invalidated iterators stored in fixed_ IntervalPtrs. Reset them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70378 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 07:16:34 +00:00
Chris Lattner
672452d5a0 Disable the load-shrinking optimization from looking at
anything larger than 64-bits, avoiding a crash.  This should
really be fixed to use APInts, though type legalization happens
to help us out and we get good code on the attached testcase at
least.

This fixes rdar://6836460


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70360 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 03:45:07 +00:00
Bill Wendling
be8cc2a3de Second attempt:
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70343 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 00:15:41 +00:00
Anton Korobeynikov
573c92d8ba Properly print 'P' modifier on inline asm memory operands.
This should fix PR3379 and PR4064.
Patch inspired by Edwin Török!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70328 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-28 21:49:33 +00:00
Evan Cheng
30590f5023 Fix PR4034. Bug in LiveInterval::join when it's compacting new valno's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70291 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-28 06:24:09 +00:00
Evan Cheng
e9ccb3a7d4 Fix for PR4051. When 2address pass delete an instruction, update kill info when necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70279 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-28 02:12:36 +00:00
Bill Wendling
c69d56f115 r70270 isn't ready yet. Back this out. Sorry for the noise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70275 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-28 01:04:53 +00:00
Bill Wendling
2e9d5f912a Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70270 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-28 00:21:31 +00:00
Evan Cheng
c45288e06b Fix PR4076. Correctly create live interval of physical register with two-address update.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70245 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27 20:42:46 +00:00
Dan Gohman
c7749b747e Permit ChangeCompareStride to rewrite a comparison when the factor
between the comparison's iv stride and the candidate stride is
exactly -1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70244 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27 20:35:32 +00:00
Dan Gohman
01ecca20bf Teach getZeroExtendExpr and getSignExtendExpr to use trip-count
information to simplify [sz]ext({a,+,b}) to {zext(a),+,[zs]ext(b)},
as appropriate.

These functions and the trip count code each call into the other, so
this requires careful handling to avoid infinite recursion. During
the initial trip count computation, conservative SCEVs are used,
which are subsequently discarded once the trip count is actually
known.

Among other benefits, this change lets LSR automatically eliminate
some unnecessary zext-inreg and sext-inreg operation where the
operand is an induction variable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70241 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27 20:16:15 +00:00
Nate Begeman
5f96943e01 Revert accidental testcase reduction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70226 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27 18:42:40 +00:00
Nate Begeman
9008ca6b6b 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
PR2957

ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask.  A value of -1 represents UNDEF.

In addition to eliminating the creation of illegal BUILD_VECTORS just to 
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70225 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27 18:41:29 +00:00
Evan Cheng
d521bc983b Fix PR4056. It's possible a physical register def is dead if its implicit use is deleted by two-address pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70213 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27 17:36:47 +00:00
Dan Gohman
f45728dae3 Fix the syntax for a PR number in a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70208 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27 15:08:34 +00:00
Dan Gohman
c7b3444095 When transforming sext(trunc(load(x))) into sext(smaller load(x)),
the trunc is directly replaced with the smaller load, so don't
try to create a new sext node. This fixes PR4050.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70179 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27 02:00:55 +00:00
Evan Cheng
0adb527d16 Do not share a single unknown val# for all the live ranges merged into a physical sub-register live interval. When coalescer is merging in clobbered virtaul register live interval into a physical register live interval, give each virtual register val# a separate val# in the physical register live interval. Otherwise, the coalescer would have lost track of the definitions information it needs to make correct coalescing decisions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70026 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-25 09:25:19 +00:00
Dale Johannesen
2f91f30b93 Fix PR 4057, a crash doing float->char const folding.
This particular one is undefined behavior (although this
isn't related to the crash), so it will no longer do it
at compile time, which seems better.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69990 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-24 21:34:13 +00:00
Rafael Espindola
15f1b66d64 Fix PR 4004 by including the call to __tls_get_addr in X86tlsaddr. This is not
very elegant, but neither is the tls specification :-(



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69968 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-24 12:59:40 +00:00
Rafael Espindola
15684b2955 Revert 69952. Causes testsuite failures on linux x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69967 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-24 12:40:33 +00:00
Nate Begeman
b706d29f9c PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask.  A value of -1 represents UNDEF.

In addition to eliminating the creation of illegal BUILD_VECTORS just to 
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.

A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69952 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-24 03:42:54 +00:00
Dan Gohman
e41bc94bb1 Explicitly pass -tailcallopt=false to these tests so that they
work as intended no matter what the default setting of that
option is.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69911 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23 19:39:41 +00:00
Evan Cheng
5b69ebac85 It has finally happened. Spiller is now using live interval info.
This fixes a very subtle bug. vr defined by an implicit_def is allowed overlap with any register since it doesn't actually modify anything. However, if it's used as a two-address use, its live range can be extended and it can be spilled. The spiller must take care not to emit a reload for the vn number that's defined by the implicit_def. This is both a correctness and performance issue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69743 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-21 22:46:52 +00:00
Evan Cheng
206d1856ad Added a linearscan register allocation optimization. When the register allocator spill an interval with multiple uses in the same basic block, it creates a different virtual register for each of the reloads. e.g.
%reg1498<def> = MOV32rm %reg1024, 1, %reg0, 12, %reg0, Mem:LD(4,4) [sunkaddr39 + 0]
        %reg1506<def> = MOV32rm %reg1024, 1, %reg0, 8, %reg0, Mem:LD(4,4) [sunkaddr42 + 0]
        %reg1486<def> = MOV32rr %reg1506
        %reg1486<def> = XOR32rr %reg1486, %reg1498, %EFLAGS<imp-def,dead>
        %reg1510<def> = MOV32rm %reg1024, 1, %reg0, 4, %reg0, Mem:LD(4,4) [sunkaddr45 + 0]

=>

        %reg1498<def> = MOV32rm %reg2036, 1, %reg0, 12, %reg0, Mem:LD(4,4) [sunkaddr39 + 0]
        %reg1506<def> = MOV32rm %reg2037, 1, %reg0, 8, %reg0, Mem:LD(4,4) [sunkaddr42 + 0]
        %reg1486<def> = MOV32rr %reg1506
        %reg1486<def> = XOR32rr %reg1486, %reg1498, %EFLAGS<imp-def,dead>
        %reg1510<def> = MOV32rm %reg2038, 1, %reg0, 4, %reg0, Mem:LD(4,4) [sunkaddr45 + 0]

From linearscan's point of view, each of reg2036, 2037, and 2038 are separate registers, each is "killed" after a single use. The reloaded register is available and it's often clobbered right away. e.g. In thise case reg1498 is allocated EAX while reg2036 is allocated RAX. This means we end up with multiple reloads from the same stack slot in the same basic block.

Now linearscan recognize there are other reloads from same SS in the same BB. So it'll "downgrade" RAX (and its aliases) after reg2036 is allocated until the next reload (reg2037) is done. This greatly increase the likihood reloads from SS are reused.

This speeds up sha1 from OpenSSL by 5.8%. It is also an across the board win for SPEC2000 and 2006.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69585 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-20 08:01:12 +00:00
Chris Lattner
9dcab2fe8e testcase for PR3898
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69473 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-18 20:49:22 +00:00
Duncan Sands
b10b5ac8d9 Don't try to make BUILD_VECTOR operands have the same
type as the vector element type: allow them to be of
a wider integer type than the element type all the way
through the system, and not just as far as LegalizeDAG.
This should be safe because it used to be this way
(the old type legalizer would produce such nodes), so
backends should be able to handle it.  In fact only
targets which have legal vector types with an illegal
promoted element type will ever see this (eg: <4 x i16>
on ppc).  This fixes a regression with the new type
legalizer (vec_splat.ll).  Also, treat SCALAR_TO_VECTOR
the same as BUILD_VECTOR.  After all, it is just a
special case of BUILD_VECTOR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69467 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-18 20:16:54 +00:00
Dale Johannesen
2cf68d4d23 Adjust XFAIL syntax, maybe that will help. The other
way worked for me...



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69414 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-18 02:01:23 +00:00
Dale Johannesen
f4948450d1 patch 69408 breaks this by removing the opportunity
for the optimization it's testing to kick in (although
it improves the code, getting rid of all spills).
I don't understand the optimization well enough to
rescue the test, so XFAILing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69409 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-18 00:11:50 +00:00
Bob Wilson
7eb793dd09 Rename file to have the correct suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69380 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 20:40:20 +00:00
Bob Wilson
1f595bb429 Use CallConvLower.h and TableGen descriptions of the calling conventions
for ARM.  Patch by Sandeep Patel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69371 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 19:07:39 +00:00
Rafael Espindola
2ee3db3003 For general dynamic TLS access we must use
leaq	foo@TLSGD(%rip), %rdi

as part of the instruction sequence. Using a register other than %rdi and then
copying it to %rdi is not valid.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69350 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 14:35:58 +00:00
Evan Cheng
276b77e66c Teach spiller to unfold instructions which modref spill slot when a scratch
register is available and when it's profitable.

e.g.
     xorq  %r12<kill>, %r13
     addq  %rax, -184(%rbp)
     addq  %r13, -184(%rbp)
==>
     xorq  %r12<kill>, %r13
     movq  -184(%rbp), %r12
     addq  %rax, %r12
     addq  %r13, %r12
     movq  %r12, -184(%rbp)

Two more instructions, but fewer memory accesses. It can also open up
opportunities for more optimizations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69341 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 01:29:40 +00:00
Rafael Espindola
7c36683fa3 fix PR3995. A scale must be 1, 2, 4 or 8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69284 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-16 12:34:53 +00:00
Dan Gohman
2d1be87ee4 Expand GEPs in ScalarEvolution expressions. SCEV expressions can now
have pointer types, though in contrast to C pointer types, SCEV
addition is never implicitly scaled. This not only eliminates the
need for special code like IndVars' EliminatePointerRecurrence
and LSR's own GEP expansion code, it also does a better job because
it lets the normal optimizations handle pointer expressions just
like integer expressions.

Also, since LLVM IR GEPs can't directly index into multi-dimensional
VLAs, moving the GEP analysis out of client code and into the SCEV
framework makes it easier for clients to handle multi-dimensional
VLAs the same way as other arrays.

Some existing regression tests show improved optimization.
test/CodeGen/ARM/2007-03-13-InstrSched.ll in particular improved to
the point where if-conversion started kicking in; I turned it off
for this test to preserve the intent of the test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69258 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-16 03:18:22 +00:00
Dan Gohman
5b9c31841f Fix the RUN lines so that this test actually tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69096 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-14 22:50:17 +00:00
Dan Gohman
62ad138d70 For the h-register addressing-mode trick, use the correct value for
any non-address uses of the address value. This fixes 186.crafty.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69094 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-14 22:45:05 +00:00
Dan Gohman
5ec3b427c8 When the result of an EXTRACT_SUBREG, INSERT_SUBREG, or SUBREG_TO_REG
operator is used by a CopyToReg to export the value to a different
block, don't reuse the CopyToReg's register for the subreg operation
result if the register isn't precisely the right class for the
subreg operation.

Also, rename the h-registers.ll test, now that there are more
than one.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69087 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-14 22:17:14 +00:00
Evan Cheng
b3f5bfe37f Some of GR8_NOREX registers are only available in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69049 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-14 16:57:43 +00:00
Dale Johannesen
442b7bfc80 Use the output of the asm so the optimizer won't
delete it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69018 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-14 01:51:40 +00:00
Evan Cheng
87d696a4d2 Fix PR3934 part 2. findOnlyInterestingUse() was not setting IsCopy and IsDstPhys which are returned by value and used by callee. This happened to work on the earlier test cases because of a logic error in the caller side.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69006 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-14 00:32:25 +00:00
Evan Cheng
3005ed6048 PR3934: Fix a bogus two-address pass assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68979 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 20:04:24 +00:00
Dan Gohman
21e3dfbc86 Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
   and in some cases a temporary register.
 - Add address-mode matching for turning (X>>(8-n))&(255<<n), where
   n is a valid address-mode scale value, into an h-register extract
   and a scaled-offset address.
 - Replace X86's MOV32to32_ and related instructions with the new
   target-independent COPY_TO_SUBREG instruction.

On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.

These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
Rafael Espindola
7ff5bff45e X86-64 TLS support for local exec and initial exec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68947 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 13:02:49 +00:00
Chris Lattner
266c7bbbbc Add a new "available_externally" linkage type. This is intended
to support C99 inline, GNU extern inline, etc.  Related bugzilla's
include PR3517, PR3100, & PR2933.  Nothing uses this yet, but it
appears to work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68940 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 05:44:34 +00:00
Rafael Espindola
b215776fa1 In X86DAGToDAGISel::MatchWrapper, if base or index are set, avoid matching
only if symbolic addresses are RIP relatives.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68924 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-12 23:00:38 +00:00