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Author SHA1 Message Date
Andrew Lenharth
afe3f49815 mul by const conversion sequences. more coming soon 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27368 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-03 03:18:59 +00:00
Andrew Lenharth
cf4fb61f6c back this out 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27367 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-03 03:16:50 +00:00
Andrew Lenharth
0fb79fa078 test some more mul by constant removal 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27366 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-03 03:16:09 +00:00
Andrew Lenharth
f80d2f61af Make sure mul by constant 5 is turned into a s4addq 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27365 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 21:47:07 +00:00
Andrew Lenharth
50a0d426e8 This should be a win of every arch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27364 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 21:42:45 +00:00
Andrew Lenharth
ccd9f98bcb This makes McCat/12-IOtest go 8x faster or so 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27363 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 21:08:39 +00:00
Andrew Lenharth
ed5d1afffb This will be needed soon 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27362 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 20:13:57 +00:00
Reid Spencer
0c5f7931d9 For PR722: 
Change the check for llvm-gcc from using LLVMGCCDIR to LLVMGCC. This checks
for the actual tool rather than the directory in which the tool resides. In
the case of this bug, it is possible that the directory exists but that the
tools in that directory do not. This fix should avoid the makefile from
erroneously proceeding without the actual tools being available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27361 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 14:34:26 +00:00
Chris Lattner
220d2b89d6 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27360 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 07:20:00 +00:00
Chris Lattner
bbe77de450 Inform the dag combiner that the predicate compares only return a low bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27359 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 06:26:07 +00:00
Chris Lattner
1b5232a937 relax assertion 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27358 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 06:19:46 +00:00
Chris Lattner
1482b5fc7a Allow targets to compute masked bits for intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27357 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 06:15:09 +00:00
Chris Lattner
350bec0fb9 Add a little dag combine to compile this: 
int %AreSecondAndThirdElementsBothNegative(<4 x float>* %in) {
entry:
        %tmp1 = load <4 x float>* %in           ; <<4 x float>> [#uses=1]
        %tmp = tail call int %llvm.ppc.altivec.vcmpgefp.p( int 1, <4 x float> < float 0x7FF8000000000000, float 0.000000e+00, float 0.000000e+00, float 0x7FF8000000000000 >, <4 x float> %tmp1 )           ; <int> [#uses=1]
        %tmp = seteq int %tmp, 0                ; <bool> [#uses=1]
        %tmp3 = cast bool %tmp to int           ; <int> [#uses=1]
        ret int %tmp3
}

into this:

_AreSecondAndThirdElementsBothNegative:
        mfspr r2, 256
        oris r4, r2, 49152
        mtspr 256, r4
        li r4, lo16(LCPI1_0)
        lis r5, ha16(LCPI1_0)
        lvx v0, 0, r3
        lvx v1, r5, r4
        vcmpgefp. v0, v1, v0
        mfcr r3, 2
        rlwinm r3, r3, 27, 31, 31
        mtspr 256, r2
        blr

instead of this:

_AreSecondAndThirdElementsBothNegative:
        mfspr r2, 256
        oris r4, r2, 49152
        mtspr 256, r4
        li r4, lo16(LCPI1_0)
        lis r5, ha16(LCPI1_0)
        lvx v0, 0, r3
        lvx v1, r5, r4
        vcmpgefp. v0, v1, v0
        mfcr r3, 2
        rlwinm r3, r3, 27, 31, 31
        xori r3, r3, 1
        cntlzw r3, r3
        srwi r3, r3, 5
        mtspr 256, r2
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27356 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 06:11:11 +00:00
Chris Lattner
4132afb0d2 vector casts of casts are eliminable. Transform this: 
%tmp = cast <4 x uint> %tmp to <4 x int>                ; <<4 x int>> [#uses=1]
        %tmp = cast <4 x int> %tmp to <4 x float>               ; <<4 x float>> [#uses=1]

into:

        %tmp = cast <4 x uint> %tmp to <4 x float>              ; <<4 x float>> [#uses=1]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27355 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 05:43:13 +00:00
Chris Lattner
a3124a3d1e vector casts never reinterpret bits 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27354 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 05:40:28 +00:00
Chris Lattner
a1c3538537 Allow transforming this: 
%tmp = cast <4 x uint>* %testData to <4 x int>*         ; <<4 x int>*> [#uses=1]
        %tmp = load <4 x int>* %tmp             ; <<4 x int>> [#uses=1]

to this:

        %tmp = load <4 x uint>* %testData               ; <<4 x uint>> [#uses=1]
        %tmp = cast <4 x uint> %tmp to <4 x int>                ; <<4 x int>> [#uses=1]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27353 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 05:37:12 +00:00
Chris Lattner
82ed58f9c4 Turn altivec lvx/stvx intrinsics into loads and stores. This allows the 
elimination of one load from this:

int AreSecondAndThirdElementsBothNegative( vector float *in ) {
#define QNaN 0x7FC00000
const vector unsigned int testData = (vector unsigned int)( QNaN, 0, 0, QNaN );
vector float test = vec_ld( 0, (float*) &testData );
return ! vec_any_ge( test, *in );
}

Now generating:

_AreSecondAndThirdElementsBothNegative:
        mfspr r2, 256
        oris r4, r2, 49152
        mtspr 256, r4
        li r4, lo16(LCPI1_0)
        lis r5, ha16(LCPI1_0)
        addi r6, r1, -16
        lvx v0, r5, r4
        stvx v0, 0, r6
        lvx v1, 0, r3
        vcmpgefp. v0, v0, v1
        mfcr r3, 2
        rlwinm r3, r3, 27, 31, 31
        xori r3, r3, 1
        cntlzw r3, r3
        srwi r3, r3, 5
        mtspr 256, r2
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27352 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 05:30:25 +00:00
Chris Lattner
02b72556d7 Remove done item 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27351 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 05:28:54 +00:00
Jeff Cohen
b196ac846d Fix tablegen related dependencies in Visual Studio. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27350 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 05:20:53 +00:00
Chris Lattner
4aab2f4ab5 Implement promotion for EXTRACT_VECTOR_ELT, allowing v16i8 multiplies to work with PowerPC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27349 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 05:06:04 +00:00
Chris Lattner
c55bfd0265 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27348 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 03:59:11 +00:00
Chris Lattner
bc70cf8be9 Implement the Expand action for binary vector operations to break the binop 
into elements and operate on each piece.  This allows generic vector integer
multiplies to work on PPC, though the generated code is horrible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27347 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 03:57:31 +00:00
Chris Lattner
e58a780166 Intrinsics that just load from memory can be treated like loads: they don't 
have to serialize against each other.  This allows us to schedule lvx's
across each other, for example.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27346 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 03:41:14 +00:00
Chris Lattner
5348e393df Adjust the Intrinsics.gen interface a little bit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27345 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 03:35:30 +00:00
Chris Lattner
7224f84c15 Adjust to change in Intrinsics.gen interface. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27344 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 03:35:01 +00:00
Chris Lattner
edab1b9133 Constant fold all of the vector binops. This allows us to compile this: 
"vector unsigned char mergeLowHigh = (vector unsigned char)
( 8, 9, 10, 11, 16, 17, 18, 19, 12, 13, 14, 15, 20, 21, 22, 23 );
vector unsigned char mergeHighLow = vec_xor( mergeLowHigh, vec_splat_u8(8));"

aka:

void %test2(<16 x sbyte>* %P) {
  store <16 x sbyte> cast (<4 x int> xor (<4 x int> cast (<16 x ubyte> < ubyte 8, ubyte 9, ubyte 10, ubyte 11, ubyte 16, ubyte 17, ubyte 18, ubyte 19, ubyte 12, ubyte 13, ubyte 14, ubyte 15, ubyte 20, ubyte 21, ubyte 22, ubyte 23 > to <4 x int>), <4 x int> cast (<16 x sbyte> < sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8 > to <4 x int>)) to <16 x sbyte>), <16 x sbyte> * %P
  ret void
}

into this:

_test2:
        mfspr r2, 256
        oris r4, r2, 32768
        mtspr 256, r4
        li r4, lo16(LCPI2_0)
        lis r5, ha16(LCPI2_0)
        lvx v0, r5, r4
        stvx v0, 0, r3
        mtspr 256, r2
        blr

instead of this:

_test2:
        mfspr r2, 256
        oris r4, r2, 49152
        mtspr 256, r4
        li r4, lo16(LCPI2_0)
        lis r5, ha16(LCPI2_0)
        vspltisb v0, 8
        lvx v1, r5, r4
        vxor v0, v1, v0
        stvx v0, 0, r3
        mtspr 256, r2
        blr

... which occurs here:
http://developer.apple.com/hardware/ve/calcspeed.html


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27343 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 03:25:57 +00:00
Chris Lattner
5e46a19ec8 Add a new -view-legalize-dags command line option 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27342 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 03:07:27 +00:00
Chris Lattner
6258fb2592 Implement constant folding of bit_convert of arbitrary constant vbuild_vector nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27341 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 02:53:43 +00:00
Chris Lattner
5e08a11039 These entries already exist 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27340 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 02:51:27 +00:00
Chris Lattner
97d23335ad Add some missing node names 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27339 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 02:41:18 +00:00
Chris Lattner
885a87ef85 simplify this method 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27338 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 02:28:52 +00:00
Chris Lattner
5295122b0d New note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27337 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 01:47:20 +00:00
Chris Lattner
4460f4058f Constant fold casts from things like <4 x int> -> <4 x uint>, likewise int<->fp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27336 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 01:38:28 +00:00
Chris Lattner
541f91b17c Custom lower all BUILD_VECTOR's so that we can compile vec_splat_u8(8) into 
"vspltisb v0, 8" instead of a constant pool load.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27335 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 00:43:36 +00:00
Chris Lattner
f8814cf8b8 Prefer larger register classes over smaller ones when a register occurs in 
multiple register classes.  This fixes PowerPC/2006-04-01-FloatDoubleExtend.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27334 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 00:24:45 +00:00
Chris Lattner
4502e13c9b New testcase that crashes the compiler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27333 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-02 00:23:59 +00:00
Chris Lattner
3805dea3fe add valuemapper support for inline asm 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27332 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-01 23:17:11 +00:00
Chris Lattner
c3837d4917 Implement vnot using VNOR instead of using 'vspltisb v0, -1' and vxor 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27331 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-01 22:41:47 +00:00
Chris Lattner
ae1ab3989c Fix InstCombine/2006-04-01-InfLoop.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27330 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-01 22:05:01 +00:00
Chris Lattner
ff1a14aba9 New testcase that caused instcombine to infinitely loop (with my recent 
patch), distilled from Applications/JM/ldecod


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27329 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-01 22:04:40 +00:00
Chris Lattner
64daab56c2 Fold A^(B&A) -> (B&A)^A 
Fold (B&A)^A == ~B & A

This implements InstCombine/xor.ll:test2[56]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27328 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-01 08:03:55 +00:00
Chris Lattner
1d4b07cfee new testcases 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27327 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-01 08:02:51 +00:00
Chris Lattner
60a05cc118 Fix Transforms/IndVarsSimplify/2006-03-31-NegativeStride.ll and 
PR726 by performing consistent signed division, not consistent unsigned
division when evaluating scev's.  Do not touch udivs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27326 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-01 04:48:52 +00:00
Chris Lattner
b076783e7d new testcase for PR726 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27325 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-01 04:47:17 +00:00
Chris Lattner
eaa7c06d86 ADd a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27324 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-01 04:08:29 +00:00
Chris Lattner
6e6b0da303 If we can look through vector operations to find the scalar version of an 
extract_element'd value, do so.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27323 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 23:01:56 +00:00
Chris Lattner
348ba3f9bf Shrinkify some more intrinsic definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27322 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 22:41:56 +00:00
Evan Cheng
67d3d4c085 An entry about packed type alignments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27321 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 22:35:14 +00:00
Chris Lattner
6cea814f2c Pull operand asm string into base class, shrinkifying intrinsic definitions. 
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27320 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 22:34:05 +00:00
Evan Cheng
e668bdaa52 TargetData.cpp::getTypeInfo() was returning alignment of element type as the 
alignment of a packed type. This is obviously wrong. Added a workaround that
returns the size of the packed type as its alignment. The correct fix would
be to return a target dependent alignment value provided via TargetLowering
(or some other interface).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27319 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 22:33:42 +00:00