Eric Christopher
6d1cd1cd04
Separate out the AES-NI instructions from the SSE4.2 instructions. Add
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a new subtarget option for AES and check for the support. Add "westmere"
line of processors and add AES-NI support to the core i7.
Add a couple of TODOs for information I couldn't verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100231 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 21:54:27 +00:00
Evan Cheng
48c58bb861
Nehalem unaligned memory access is fast.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100089 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-01 05:58:17 +00:00
Evan Cheng
bdc652bab8
Turning off post-ra scheduling for x86. It isn't a consistent win.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98810 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 06:55:42 +00:00
Chris Lattner
314a113184
add support for pentium class CPUs which do not have cmov,
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PR4841. Patch by Craig Smith!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 18:31:44 +00:00
Mikhail Glushenkov
5d96eb8671
80-col violations/trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-28 22:54:30 +00:00
Anton Korobeynikov
ebb0c2b287
Setup correct data layout to match gcc's expectations on mingw32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95981 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-12 15:28:56 +00:00
Duncan Sands
990c4b87e3
Fix typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93235 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-12 08:30:46 +00:00
Duncan Sands
e2de606e0b
Tweak commit 91745, which changed target data for both Mingw and Cygwin,
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to not touch Cygwin: the change caused llvm-gcc build failures due to
long double getting the wrong size. Patch by Aaron Gray.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93234 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-12 08:21:07 +00:00
David Greene
95eb2eeea6
Implement a feature (-vector-unaligned-mem) to allow targets to
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ignore alignment requirements for SIMD memory operands. This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93151 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-11 16:29:42 +00:00
Evan Cheng
b1f4981333
Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91910 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22 17:47:23 +00:00
Anton Korobeynikov
e9ec6ad1ba
Bump alignment requirements for windows targets to achieve compartibility with vcpp.
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Based on patch by Michael Beck!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91745 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-19 02:04:23 +00:00
Evan Cheng
400073d546
On recent Intel u-arch's, folding loads into some unary SSE instructions can
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be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.
movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0
instead of
cvtss2sd (%rdi), %xmm0
An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91672 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 07:40:29 +00:00
Dan Gohman
29cbade25a
Target-independent support for TargetFlags on BlockAddress operands,
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and support for blockaddresses in x86-32 PIC mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89506 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 23:18:13 +00:00
David Goodwin
87d21b92fc
Allow target to specify regclass for which antideps will only be broken along the critical path.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88682 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 19:52:48 +00:00
David Goodwin
c2e8a7e8d2
Fixed to address code review. No functional changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86634 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-10 00:48:55 +00:00
David Goodwin
0855dee564
Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-10 00:15:47 +00:00
Chris Lattner
59a9178fbe
indicate what the native integer types for the target are.
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Please verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86397 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 19:07:32 +00:00
Evan Cheng
c869d063d4
X86 needs critical path anti-dependency breaking.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84931 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-23 05:57:35 +00:00
David Goodwin
4c3715c2e5
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 23:19:17 +00:00
Evan Cheng
d36076e4a3
Turn on post-alloc scheduling for x86.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84431 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-18 19:57:27 +00:00
Evan Cheng
eb6e1daa43
Oops. I forgot to change the tests first. Disable post-alloc scheduling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84425 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-18 18:31:31 +00:00
Evan Cheng
ff89dcb06f
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
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stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2 .
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-18 18:16:27 +00:00
Evan Cheng
fa16354e03
Change createPostRAScheduler so it can be turned off at llc -O1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84273 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-16 21:06:15 +00:00
Evan Cheng
79f7400e4f
Remove X86Subtarget::IsLinux. It's no longer being used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84200 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-15 20:23:21 +00:00
Chris Lattner
a76e3fc131
rearrange X86ATTAsmPrinter::doFinalization, making a scan of
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the global variable list only happen for COFF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82010 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-16 05:20:33 +00:00
Daniel Dunbar
848113833f
Make these functions static and local.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80892 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-03 05:47:34 +00:00
Evan Cheng
d0da6ff3ad
X86JITInfo::getLazyResolverFunction() should not read cpu id to determine whether sse is available. Just use consult subtarget.
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No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80880 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-03 04:37:05 +00:00
Chris Lattner
700841617a
Add support for modeling whether or not the processor has support for
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conditional moves as a subtarget feature. This is the easy part of
PR4841.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80763 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-02 05:53:04 +00:00
Chris Lattner
ce914b8f94
change the -x86-asm-syntax=intel/att flag to be in X86TAI
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instead of X86 Subtarget. This elimianates dependencies on
X86Subtarget from X86TAI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78746 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 23:01:09 +00:00
Daniel Dunbar
3be03406c9
Normalize Subtarget constructors to take a target triple string instead of
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Module*.
Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77918 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-02 22:11:08 +00:00
Chris Lattner
e2c920845a
remove the now-dead TM argument to these methods.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75276 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 21:00:45 +00:00
Chris Lattner
8097b65c43
make PIC vs DynamicNoPIC be explicit in PICStyles.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75275 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 20:58:47 +00:00
Chris Lattner
3b67e9ba01
add a couple of predicates to test for "stub style pic in PIC mode" and "stub style pic in dynamic-no-pic" mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75273 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 20:47:30 +00:00
Chris Lattner
0d786dd954
simplify fast isel by using ClassifyGlobalReference. This
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elimiantes the last use of GVRequiresExtraLoad, so delete it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75244 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 07:48:51 +00:00
Chris Lattner
dfed413ef6
eliminate GVRequiresRegister, replacing it with predicates we
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need for other purposes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75243 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 07:38:24 +00:00
Chris Lattner
d392bd97c8
move some classification logic around. Now GVRequiresExtraLoad
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is just a trivial wrapper around "ClassifyGlobalReference", which
stole a ton of logic from LowerGlobalAddress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75237 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 07:20:05 +00:00
Chris Lattner
ed0dca6a5d
GVRequiresExtraLoad is now never used for calls, simplify it based on this.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75232 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 05:52:02 +00:00
Chris Lattner
754b7650c2
actually, just eliminate PCRelGVRequiresExtraLoad. It makes the code
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more complex and slow than just directly testing what we care about.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75231 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 05:48:03 +00:00
Chris Lattner
e6c07b52e7
There is only one case where GVRequiresExtraLoad returns true for calls:
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split its handling out to PCRelGVRequiresExtraLoad, and simplify code
based on this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75230 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 05:45:15 +00:00
Chris Lattner
04b304caf6
the "isDirectCall" operand of GVRequiresRegister is always false, eliminate it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75229 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 05:37:11 +00:00
Chris Lattner
e4df756289
When in -static mode, force the PIC style to none. Doing this requires fixing
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code which conflated RIPRel PIC with x86-64. Fix these to just check for X86-64
directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75092 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-09 03:15:51 +00:00
David Greene
640a0c1477
Fix a subtarget feature bug.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74428 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 16:51:01 +00:00
David Greene
343dadbb36
Add feature flags for AVX and FMA and fix some SSE4A feature flag
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initialization problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74350 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-26 22:46:54 +00:00
Chris Lattner
aecaa1f143
cosmetic changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73836 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-21 01:27:55 +00:00
Stefanus Du Toit
8cf5ab153d
Update CPU capabilities for AMD machines
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- added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and
barcelona with appropriate sse3/4a levels
- added FeatureSSE4A for amdfam10 processors
in X86Subtarget:
- added hasSSE4A
- updated AutoDetectSubtargetFeatures to detect SSE4A
- updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and
family 10h as amdfam10
New processor names match those used by gcc.
Patch by Paul Redmond!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72434 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-26 21:04:35 +00:00
Anton Korobeynikov
41a024385f
Propagate CPU string out of SubtargetFeatures
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-23 19:50:50 +00:00
Evan Cheng
d7f666a869
Try again. Allow call to immediate address for ELF or when in static relocation mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72160 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-20 04:53:57 +00:00
Dan Gohman
d68a07650c
Tidy up #includes, deleting a bunch of unnecessary #includes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-05 17:59:02 +00:00
Evan Cheng
ccb6976a69
Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61557 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-02 05:35:45 +00:00
Dan Gohman
8749b61178
Add initial support for back-scheduling address computations,
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especially in the case of addresses computed from loop induction
variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61075 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-16 03:35:01 +00:00