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4316 Commits

Author SHA1 Message Date
Sylvestre Ledru
94c22716d6 Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 10:14:43 +00:00
Sylvestre Ledru
7e2c793a2b Fix a typo 'iff' => 'if' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 09:59:43 +00:00
Chad Rosier
2590c2e1e9 Rather then have a wrapper function, have tblgen instantiate the implementation. 
Also remove an unused argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164567 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-24 22:57:55 +00:00
Chad Rosier
00796a1b15 Rather then have a wrapper function, have tblgen instantiate the implementation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164548 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-24 19:32:29 +00:00
Andrew Trick
9264988311 Machine Model (-schedmodel only). Added SchedAliases. 
Allow subtargets to tie SchedReadWrite types to processor specific
sequences or variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164451 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-22 02:24:21 +00:00
Chad Rosier
d717a066c6 [ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164420 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-21 22:21:26 +00:00
Chad Rosier
6018944afd Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164406 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-21 19:25:59 +00:00
Dmitri Gribenko
9d227af8f7 Clarify comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164371 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-21 15:26:34 +00:00
Micah Villmow
3e9b6db60f Add in new data types that are used by AMDIL/ANL among others. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164261 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-19 22:47:07 +00:00
Owen Anderson
eb79b545fc Soften the pattern-can-never-match error in TableGen into a warning. This pattern can be very useful in cases where you want to define a multiclass that covers both commutative and non-commutative operators (say, add and sub). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164256 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-19 22:15:06 +00:00
Craig Topper
8a312fb3aa Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164204 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-19 06:37:45 +00:00
Andrew Trick
3b8fb648c6 SchedMachineModel: compress the CPU's WriteLatencyTable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164199 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-19 04:43:19 +00:00
Sean Silva
b2df610b44 Iterate deterministicaly over ClassInfo*'s 
Fixes an observed instance of nondeterministic TableGen output.

Review by Jakob.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164191 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-19 01:47:03 +00:00
Sean Silva
decfdf548b Iterate deterministically over register classes 
Fixes an observed instance of nondeterministic TableGen output.

Review by Jakob.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164190 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-19 01:47:01 +00:00
Sean Silva
90fee07298 Refactor Record* by-ID comparator to Record.h 
This is a generally useful utility; there's no reason to have it hidden
in CodeGenDAGPatterns.cpp.

Also, rename it to fit the other comparators in Record.h

Review by Jakob.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164189 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-19 01:47:00 +00:00
Benjamin Kramer
30ce40e3f7 FileCheck: Fix off-by-one bug that made CHECK-NOT: ignore the next character after the colon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164165 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-18 20:51:39 +00:00
Craig Topper
3a36444366 Make custom operand parsing mnemonic indices use the same mnemonic table as the match table. Reorder fields in OperandMatchEntry to provide the least amount of padding for in tree targets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164109 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-18 07:02:21 +00:00
Craig Topper
fee7f01d1e Use variable type for index into mnemonic table. Shrinks size of index field on in tree targets. Saving static data space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164108 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-18 06:10:45 +00:00
Andrew Trick
34aadd6334 Replaced ReInitMCSubtargetInfo with InitMCProcessor. 
Now where we used to call ReInitMCSubtargetInfo, we actually recompute
the same information as InitMCSubtargetInfo instead of only setting
the feature bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164105 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-18 05:33:15 +00:00
Andrew Trick
e076bb1e93 comment typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164097 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-18 04:03:30 +00:00
Andrew Trick
e3dbc98a4f TableGen subtarget emitter. Use getSchedClassIdx. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164096 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-18 03:55:55 +00:00
Andrew Trick
4d2d1c49d7 TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164095 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-18 03:41:43 +00:00
Andrew Trick
ee290ba35a TableGen subtarget emitter. Remove unnecessary header dependence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164094 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-18 03:32:57 +00:00
Andrew Trick
e127dfd0b1 TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164092 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-18 03:18:56 +00:00
Craig Topper
b198f5c897 Mark asm matcher conversion table as const. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164088 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-18 01:41:49 +00:00
Craig Topper
be480ff607 Fix typo in comment. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164086 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-18 01:13:36 +00:00
Andrew Trick
e4095f95ac Backout the wrong subtarget emitter fix 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164078 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-17 23:14:15 +00:00
Andrew Trick
f23ddf54ea Fix release build after reverting 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164075 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-17 23:05:04 +00:00
Andrew Trick
e1b5328717 Revert r164061-r164067. Most of the new subtarget emitter. 
I have to work out the Target/CodeGen header dependencies
before putting this back.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-17 23:00:42 +00:00
Andrew Trick
a2a47d1c50 InitMCProcessor 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164066 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-17 22:19:12 +00:00
Andrew Trick
5d94082143 comment typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164064 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-17 22:19:04 +00:00
Andrew Trick
41be51b72c TableGen subtarget emitter. Use getSchedClassIdx. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164063 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-17 22:19:01 +00:00
Andrew Trick
021ba269b2 TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164062 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-17 22:18:58 +00:00
Andrew Trick
db7afac457 TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164061 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-17 22:18:55 +00:00
Andrew Trick
544c88039f TableGen subtarget emitter. Format and emit data tables for the new machine model. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164060 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-17 22:18:50 +00:00
Andrew Trick
52c3a1d654 TableGen subtarget emitter. Generate data tables for the new machine model. 
Map the CodeGenSchedule object model onto data tables. The structure
of the data tables is defined in MC, so for convenience we include
MCSchedule.h. The alternative is maintaining a redundant copy of the
table structure definitions. Mapping the object model onto data tables
is sufficiently complicated that it should not be interleaved with
emitting source code. This avoids major problem with the backend for
itinerary generation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164059 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-17 22:18:48 +00:00
Andrew Trick
40096d2693 TableGen subtarget emitter. Emit processor resources for the new machine model. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164058 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-17 22:18:45 +00:00
Andrew Trick
bc4ff6e3cf TableGen subtarget parser: Add getProcResourcesIdx(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164057 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-17 22:18:43 +00:00
Jim Grosbach
9bb938c540 TableGen: Add initializer. 
Keep GCC's warnings happy. It can't reason out that the state machine won't
ever hit the potentially uninitialized use in OPC_FilterValue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164041 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-17 18:00:53 +00:00
Axel Naumann
3780ad8b99 Fix a few vars that can end up being used without initialization. 
The cases where no initialization happens should still be checked for logic flaws.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164032 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-17 14:20:57 +00:00
Michael Liao
efd841cdc5 Fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164012 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-17 04:43:39 +00:00
Craig Topper
af8d66ce9a Add 'virtual' keywoards to output file for overridden functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164002 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-16 18:25:36 +00:00
Craig Topper
ef2340ef48 Add 'virtual' keywoards to output file for overridden functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163999 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-16 16:35:22 +00:00
Dmitri Gribenko
4e0ae44b3a Fix Doxygen issues: wrap code examples in \code and use \p to refer to 
parameters.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163984 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-15 20:22:05 +00:00
Craig Topper
5974c31acb Revert r163878 as it breaks on targets with alternate register names. Such targets do not exist in the main tree so this was not noticed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163959 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-15 01:22:42 +00:00
Andrew Trick
3cbd1786ac TableGen subtarget parser. Handle new machine model. 
Collect processor resources from the subtarget defs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163953 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-15 00:20:02 +00:00
Andrew Trick
5e613c260b TableGen subtarget parser. Handle new machine model. 
Infer SchedClasses from variants defined by the target or subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163952 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-15 00:19:59 +00:00
Andrew Trick
48605c3406 TableGen subtarget parser. Handle new machine model. 
Collect SchedClasses and SchedRW types from the subtarget defs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163951 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-15 00:19:57 +00:00
Craig Topper
f4d78241ea Allow the second opcode info table to be 8, 16, or 32-bits as needed to represent additional fragments. This recovers some space on ATT X86 syntax and PowerPC which only need 40-bits instead of 48-bits. This also increases ARM to 64-bits to fully encode all of its operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163880 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-14 08:33:11 +00:00
Craig Topper
4e5babe4f3 Reduce size of register name index tables by using uint16_t for all in tree targets. If more than 16-bits are needed for any out of tree targets, code will detect and use uint32_t instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163878 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-14 06:37:49 +00:00