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Author SHA1 Message Date
David Goodwin
9843a93e83 Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 22:19:57 +00:00
Mike Stump
e4250396ea Expand api out in the usual inserter way, though, I do have a 
question, can we get rid of the BasicBlock versions of all inserters
and use Head == 0 to indicate the old case when GetInsertBlock == 0?


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83216 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 22:08:58 +00:00
David Goodwin
471850ab84 Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83215 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 21:46:35 +00:00
Evan Cheng
10469f8e48 ARM::tPOP and tPOP_RET each has an extra writeback operand now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83214 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 20:54:53 +00:00
Jim Grosbach
95923d70d9 remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83213 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 20:45:06 +00:00
Devang Patel
af9e84701b Add support to extract lexical scope information from DebugLoc attached with an machine instruction. 
This is not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83210 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 20:31:14 +00:00
David Goodwin
c7951f8e09 Use MachineFrameInfo.getPristineRegs() to determine which callee-saved registers are available for anti-dependency breaking. Some cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83208 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 19:45:32 +00:00
Devang Patel
d38dd11e12 Record first and last instruction of a scope in DbgScope. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83207 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 18:25:23 +00:00
Dan Gohman
835b142edd Don't use identifiers that start with an underscore followed 
by a capital letter, which invokes undefined behavior.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83206 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 17:39:52 +00:00
Douglas Gregor
9c091a4846 Teach CMake to look for bidirectional_iterator, iterator, forward_iterator, uint64_t, and u_int64_t, from Yonggang Luo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83203 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 17:25:36 +00:00
Evan Cheng
714e8bc1fc Observe hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. Do not change 
operands of instructions with these properties while breaking anti-dep.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83198 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 08:26:23 +00:00
Evan Cheng
0d92f5f768 Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple, 
ld / st pairs, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83197 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 08:22:27 +00:00
Evan Cheng
799d697bf8 Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When 
set, these flags indicate the instructions source / def operands have special
register allocation requirement that are not captured in their register classes.
Post-allocation passes (e.g. post-alloc scheduler) should not change their
allocations. e.g. ARM::LDRD require the two definitions to be allocated
even / odd register pair.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83196 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 08:21:18 +00:00
Douglas Gregor
8f3ec31133 Remove GVNPRE.cpp from the CMake makefile 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83194 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 05:30:05 +00:00
Chris Lattner
99be299edb remove the GVNPRE pass. It has been subsumed by the GVN pass. 
Ok'd by Owen.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83193 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 02:18:36 +00:00
Evan Cheng
7c043d7319 Update ARM JIT emitter to account for ld/st multiple changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83192 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 01:39:21 +00:00
Evan Cheng
d20d658675 Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83191 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 01:33:39 +00:00
Devang Patel
a1434045c3 Add another MDNode into DebugLocTuple. This will be used to keep track of inlined functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83190 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 01:15:28 +00:00
Devang Patel
75549f4444 If location info is attached with an instruction then keep track of alloca slots used by a variable. This info will be used by AsmPrinter to emit debug info for variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83189 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 01:03:26 +00:00
Devang Patel
b0fdedb3fd Use MachineInstr as an processDebugLoc() argument. 
This will allow processDebugLoc() to handle scopes for DWARF debug info. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83183 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 23:12:50 +00:00
Devang Patel
3d910835fc Use MDNode * directly as an RecordSourceLine() argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83182 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 22:51:28 +00:00
Devang Patel
a63710124a Remove dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83181 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 22:43:52 +00:00
Devang Patel
ecbeb1a490 Add isFOO() helpers. Fix getDirectory() and getFilename() for DIScope. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83180 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 22:34:41 +00:00
Bob Wilson
29e066965f Use OutStreamer.SwitchSection instead of writing out textual section directives. 
Add a new TargetLoweringObjectFileMachO::getConstTextCoalSection method to
get access to that section.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83178 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 22:25:37 +00:00
Bob Wilson
812209a58c Add a new virtual EmitStartOfAsmFile method to the AsmPrinter and use this 
to emit target-specific things at the beginning of the asm output.  This
fixes a problem for PPC, where the text sections are not being kept together
as expected.  The base class doInitialization code calls DW->BeginModule()
which emits a bunch of DWARF section directives.  The PPC doInitialization
code then emits all the TEXT section directives, with the intention that they
will be kept together. But as I understand it, the Darwin assembler treats
the default TEXT section as a special case and moves it to the beginning of
the file, which means that all those DWARF sections are in the middle of
the text.  With this change, the EmitStartOfAsmFile hook is called before
the DWARF section directives are emitted, so that all the PPC text section
directives come out right at the beginning of the file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83176 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 22:06:26 +00:00
Bob Wilson
c4c39faa05 Fix a comment typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83174 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 21:44:42 +00:00
Devang Patel
4d7a2061f1 Check for null MDNode element while printing comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83172 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 21:26:51 +00:00
Bob Wilson
bc9506f5ee Fix a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83171 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 21:26:13 +00:00
Bob Wilson
b6e4742da7 The AsmPrinter base class contains a DwarfWriter member, so there's no need 
for derived AsmPrinters to add another one.  In some cases, fixing this
removes the need to override the doInitialization method.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83170 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 21:24:45 +00:00
Jeffrey Yasskin
1fb613c43d Assert that ConstantArrays are created with correctly-typed elements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83168 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 21:08:08 +00:00
Dan Gohman
5184635eda Fix this code so that it doesn't try to iterate through a std::vector 
while calling changeImmediateDominator, which removes elements from the
vector. This fixes PR5097.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83166 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 20:54:16 +00:00
Reid Kleckner
3a90c9b8ed Silence comparison always false warning in -Asserts mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83164 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 20:43:07 +00:00
Jim Grosbach
32030fe021 Add additional assert() to verify no extraneous use of a scavenged register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83163 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 20:35:36 +00:00
Devang Patel
2d5988d9ba Print tag name for MDNodes that are used to encode debug info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83160 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 20:16:54 +00:00
Reid Kleckner
c277ab08a2 Fix integer overflow in instruction scheduling. This can happen if we have 
basic blocks that are so long that their size overflows a short.

Also assert that overflow does not happen in the future, as requested by Evan.

This fixes PR4401.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83159 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 20:15:38 +00:00
Devang Patel
69cc57c325 Silence unused variable warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83151 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 17:13:41 +00:00
Jim Grosbach
460c482ed3 Clarify comment phrasing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83148 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 15:23:38 +00:00
Evan Cheng
792e1f6df9 Add a option which would move ld/st multiple pass before post-alloc scheduling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83145 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 08:53:01 +00:00
Evan Cheng
629adde699 Add a target hook to add pre- post-regalloc scheduling passes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83144 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 08:49:50 +00:00
Evan Cheng
48af260bb1 Forgot this test earlier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83143 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 08:41:27 +00:00
Chris Lattner
c32a53240a add macruby, fix a validation problem. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83142 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 06:27:22 +00:00
Nick Lewycky
483041e9ea Fix compile error as debug interface changed. 
By the way, this code is buggy. You can't keep a map<MDNode *, something>
because the MDNode may be destroyed and reused for something else.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83141 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 04:50:26 +00:00
Jim Grosbach
366e021fb2 replace TRI->isVirtualRegister() with TargetRegisterInfo::isVirtualRegister() 
per customary usage

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83137 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 01:47:59 +00:00
Jim Grosbach
d1a5ca6cb1 When checking whether we need to reserve a register for the scavenger, 
the size of the saved frame pointer needs to be taken into account.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83136 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 01:43:29 +00:00
Jim Grosbach
c732adf3a1 Add "isBarrier = 1" to return instructions. 
Patch by Sylvere Teissier.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83135 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 01:35:11 +00:00
Jim Grosbach
0a13e566ab fix compiler warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83132 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 00:37:40 +00:00
David Goodwin
413738ee8c Remove regression that requires post-RA scheduling from a target that does not use that scheduler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83128 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 00:23:57 +00:00
Bob Wilson
0fb34683b9 For Darwin, emit all the text section directives together before the dwarf 
section directives.  This causes the assembler to put the text sections at
the beginning of the object file, which helps work around a limitation of the
Darwin ARM relocations.  Radar 7255355.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83127 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 00:23:42 +00:00
Devang Patel
fdc826f6e8 Simplify. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83123 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 00:14:40 +00:00
David Goodwin
0dad89fa94 Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 00:10:16 +00:00