Commit Graph

45987 Commits

Author SHA1 Message Date
NAKAMURA Takumi
bab2d49d4a Windows/PathV2.inc: [PR8520] Recognize "NUL" as special (character) file.
FIXME: It is a temporal hack. We should detect as many "special file name" as possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127724 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 02:53:32 +00:00
NAKAMURA Takumi
bfb25cd97c Windows/Path.inc: [PR6270] PathV1::makeUnique(): Give arbitrary initial seed for workaround.
FIXME: We should use sys::fs::unique_file() in future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127723 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 02:53:24 +00:00
Jim Grosbach
124d0332db Tidy up. Whitespace and 80 column.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127721 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 01:21:55 +00:00
Devang Patel
ed4edf9e5f Do not accidently initialize NumDbgValueLost and NumDbgLineLost counts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127720 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 00:27:57 +00:00
Cameron Zwarich
85b0f468cf Only convert allocas to scalars if it is profitable. The profitability metric I
chose is having a non-memcpy/memset use and being larger than any native integer
type. Originally I chose having an access of a size smaller than the total size
of the alloca, but this caused some minor issues on the spirit benchmark where
SRoA runs again after some inlining.

This fixes <rdar://problem/8613163>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127718 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 00:13:44 +00:00
Cameron Zwarich
deac268f89 Better use initializer lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127716 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 00:13:37 +00:00
Cameron Zwarich
d4c9c3e6b9 Add a clarifying comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127715 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 00:13:35 +00:00
Johnny Chen
276f6f9cf9 There were two issues fixed:
1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
   Modify the ARMDisassemblerCore.cpp file to accomodate the change.

2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:

   imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
                                       // Encoding A1

   It has no business doing such.  Removed the offending logic.

Add test cases to arm-tests.txt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127707 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 22:27:33 +00:00
John Thompson
6046cffbaf Add scei vendor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127705 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 21:51:56 +00:00
Bill Wendling
0d4c9d94f6 The VTBL (and VTBX) instructions are rather permissive concerning the masks they
accept. If a value in the mask is out of range, it uses the value 0, for VTBL,
or leaves the value unchanged, for VTBX.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127700 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 21:15:20 +00:00
Jakob Stoklund Olesen
13ba2527f7 Trace back through sibling copies to hoist spills and find rematerializable defs.
After live range splitting, an original value may be available in multiple
registers. Tracing back through the registers containing the same value, find
the best place to insert a spill, determine if the value has already been
spilled, or discover a reaching def that may be rematerialized.

This is only the analysis part. The information is not used for anything yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127698 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 21:13:25 +00:00
Jakob Stoklund Olesen
29ef87599c Preserve both isPHIDef and isDefByCopy bits when copying parent values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127697 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 21:13:22 +00:00
Bill Wendling
a24cb40be2 Some minor cleanups based on feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127694 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 20:47:26 +00:00
Jim Grosbach
4f9fc854bc Trailing whitespae.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 20:25:54 +00:00
Cameron Zwarich
6e51c6ad9d Clean up something noticed by Fritz.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127684 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 18:42:33 +00:00
Evan Cheng
0191952296 Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127683 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 18:41:52 +00:00
Richard Osborne
59f727e57e Don't indent cases in a switch, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127681 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 15:55:30 +00:00
Richard Osborne
8ae8cf4559 On the XCore the scavenging slot should be closest to the SP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127680 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 15:10:11 +00:00
Richard Osborne
5aad8b3e78 Add XCore intrinsics for getps, setps, setsr and clrsr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 13:45:47 +00:00
Justin Holewinski
625eec10fe PTX: Set PTX 2.0 as the minimum supported version
- Remove PTX 1.4 code generation
- Change type of intrinsics to .v4.i32 instead of .v4.i16
- Add and/or/xor integer instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127677 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 13:24:15 +00:00
Duncan Sands
36b8e43a3e Silence compiler warning about case values not being in the enumerated type
MCFixupKind.  This is the same technique that is used elsewhere in MC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127676 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 08:54:51 +00:00
Duncan Sands
75548de301 Avoid a compiler warning about reg possibly being used uninitialized
when building with assertions disabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 08:41:24 +00:00
Cameron Zwarich
838b97edfa Do not add PHIs with no users when creating LCSSA form. Patch by Andrew Clinton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127674 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 07:41:25 +00:00
Nick Lewycky
42e72ca3d0 Add C++ global operator {new,new[],delete,delete[]}(unsigned {int,long}) to the
memory builtins as equivalent to malloc/free.

This is different from any attribute we have. For example, you can delete the
allocators when their result is unused, but you can't collapse two calls to the
same function, even if no global/memory state has changed in between. The
noalias return states that the result does not alias any other pointer, but
instcombine optimizes malloc() as though the result is non-null for the purpose
of eliminating unused pointers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127673 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 07:31:32 +00:00
Evan Cheng
d158fba3e4 Add a peephole optimization to optimize pairs of bitcasts. e.g.
v2 = bitcast v1
...
v3 = bitcast v2
...
   = v3
=>
v2 = bitcast v1
...
   = v1
if v1 and v3 are of in the same register class.

bitcast between i32 and fp (and others) are often not nops since they
are in different register classes. These bitcast instructions are often
left because they are in different basic blocks and cannot be
eliminated by dag combine.

rdar://9104514


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127668 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 05:13:13 +00:00
Eli Friedman
b1a6eab655 PR9450: Make switch optimization in SimplifyCFG not dependent on the ordering
of pointers in an std::map.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127650 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 02:23:35 +00:00
Evan Cheng
bf34a5ec22 sext(undef) = 0, because the top bits will all be the same.
zext(undef) = 0, because the top bits will be zero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127649 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 02:22:10 +00:00
Sean Callanan
f88896b2a9 Enabled disassembler support for AVX instructions
in the instruction tables and fixed a few bugs that
were causing decode conflicts.  Rudimentary tests
are coming up in the next patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127646 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 01:28:15 +00:00
Sean Callanan
a21e2eae3d X86 table-generator and disassembler support for the AVX
instruction set.  This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures.  Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127644 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 01:23:15 +00:00
Andrew Trick
4dbe200b2d Remove getMinusSCEVForExitTest().
This function performed acrobatics to prove no-self-wrap, which we now
have for free.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127643 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 01:16:14 +00:00
Johnny Chen
085ea1b633 Fixed an ARM disassembler bug where it does not handle STRi12 correctly because an extra
register operand was erroneously added.  Remove an incorrect assert which triggers the bug.

rdar://problem/9131529


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 01:13:17 +00:00
Bill Wendling
28cc1aa3a7 There are some situations which can cause the URoR hack to infinitely recurse
and then go kablooie. The problem was that it was tracking the PHI nodes anew
each time into this function. But it didn't need to. And because the recursion
didn't know that a PHINode was visited before, it would go ahead and call
itself.

There is a testcase, but unfortunately it's too big to add. This problem will go
away with the EH rewrite.
<rdar://problem/8856298>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127640 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 01:03:17 +00:00
Andrew Trick
c343c1e27e Propagate SCEV no-wrap flags whenever possible.
This needs review.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127638 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 00:37:00 +00:00
Jim Grosbach
5edf24efac Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches.
Also more cleanly separate the ARM vs. Thumb functionality. Previously, the
encoding would be incorrect for some Thumb instructions (the indirect calls).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127637 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 00:30:40 +00:00
Eric Christopher
b9b80c3268 If we don't know how long a string is we can't fold an _chk version to the
normal version.

Fixes rdar://9123638


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 00:25:41 +00:00
Bill Wendling
69a05a7b92 Generate a VTBL instruction instead of a series of loads and stores when we
can. As Nate pointed out, VTBL isn't super performant, but it *has* to be better
than this:

_shuf:
@ BB#0:       @ %entry
  push        {r4, r7, lr}
  add         r7, sp, #4
  sub         sp, #12
  mov         r4, sp
  bic         r4, r4, #7
  mov         sp, r4
  mov         r2, sp
  vmov        d16, r0, r1
  orr         r0, r2, #6
  orr         r3, r2, #7
  vst1.8      {d16[0]}, [r3]
  vst1.8      {d16[5]}, [r0]
  subs        r4, r7, #4
  orr         r0, r2, #5
  vst1.8      {d16[4]}, [r0]
  orr         r0, r2, #4
  vst1.8      {d16[4]}, [r0]
  orr         r0, r2, #3
  vst1.8      {d16[0]}, [r0]
  orr         r0, r2, #2
  vst1.8      {d16[2]}, [r0]
  orr         r0, r2, #1
  vst1.8      {d16[1]}, [r0]
  vst1.8      {d16[3]}, [r2]
  vldr.64     d16, [sp]
  vmov        r0, r1, d16
  mov         sp, r4
  pop         {r4, r7, pc}

The "illegal" testcase in vext.ll is no longer illegal.
<rdar://problem/9078775>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127630 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 23:02:38 +00:00
Jakob Stoklund Olesen
cf03e35d90 Place context in member variables instead of passing around pointers.
Use the opportunity to get rid of the trailing underscore variable names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127618 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 20:57:14 +00:00
Jakob Stoklund Olesen
766faf4b2b Rename members to match LLVM naming conventions more closely.
Remove the unused reserved_ bit vector, no functional change intended.

This doesn't break 'svn blame', this file really is all my fault.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127607 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 19:56:43 +00:00
Jim Grosbach
e2189144d4 Remove some dead patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127601 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 18:34:35 +00:00
Evan Cheng
34661e72fc BIT_CONVERT has been renamed to BITCAST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127600 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 18:19:52 +00:00
Evan Cheng
5ae1da96f2 Minor optimization. sign-ext/anyext of undef is still undef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127598 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 18:15:55 +00:00
Evan Cheng
21a6179c9d Indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127595 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 18:02:30 +00:00
Andrew Trick
a053b21177 Negating a recurrence preserves no-self-wrap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127593 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 17:38:54 +00:00
Andrew Trick
dcfd404e3c HowFarToZero can compute a trip count as long as the recurrence has no-self-wrap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 17:28:02 +00:00
Andrew Trick
3228cc259b Added SCEV::NoWrapFlags to manage unsigned, signed, and self wrap
properties.
Added the self-wrap flag for SCEV::AddRecExpr.
A slew of temporary FIXMEs indicate the intention of the no-self-wrap flag
without changing behavior in this revision.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 16:50:06 +00:00
Andrew Trick
d99b39e43b whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127589 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 16:48:10 +00:00
Justin Holewinski
ae3ce17bac PTX: Emit global arrays with proper sizes
- Emit all arrays as type .b8 and proper sizes in bytes to conform
  to the output of nvcc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127584 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 15:40:11 +00:00
Justin Holewinski
ba02495a57 PTX: Add support for sqrt/sin/cos intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 14:09:33 +00:00
Che-Liang Chiou
f78847ee7b ptx: add set.p instruction and related changes to predicate execution
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127577 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 11:26:01 +00:00
Jin-Gu Kang
948d9e7ec7 This case is solved by Scalar Replacement of Aggregates (DT) and
Early CSE pass so this patch reverts it to original source code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127574 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 01:21:00 +00:00