Commit Graph

97431 Commits

Author SHA1 Message Date
Chandler Carruth
bdd55d2bef Add the fact that we anticipate switching to use (some subset of) C++11
after the 3.4 release to the release notes. See the *lengthy* llvmdev
and cfe-dev threads on this subject. There will be more emails,
discussion and announcements, but I want to make noise in as many places
as I can to get everyone's concerns voiced and understood.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194183 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-07 00:23:08 +00:00
Vincent Lejeune
69239a98b6 R600: Fix LowerUDIVREM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194153 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 17:36:04 +00:00
Amara Emerson
1b484aba80 [AArch64] Remove NEON from "generic" CPU target.
We can change this back when NEON support is complete and ready to become
enabled by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194152 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 16:19:08 +00:00
Simon Atanasyan
4411ba06fc Add DT_VERSYM dynamic table entry tag definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194149 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 12:23:52 +00:00
Richard Sandiford
d975a82e08 [SystemZ] Handle vectors in getSetCCResultType
I don't have a standalone testcase for this, but it should allow r193676
to be reapplied.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194148 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 12:16:02 +00:00
Benjamin Kramer
02707cb98e Add test case for PR12377, it was fixed by r194116.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194147 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 11:55:41 +00:00
Peter Zotov
573a231a31 [llvm-c] Add parameter names in Target.h for C99 compliance
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194146 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 11:52:40 +00:00
Vladimir Medic
2263a2ca72 Implement gpword directive for mips, test case added. Stype changes using clang-format are also included.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 11:27:05 +00:00
Peter Zotov
54edcc2682 Add newline at EOF in DynamicLibrary.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 11:12:46 +00:00
Peter Zotov
1acb2127ba [llvm-c] Improve TargetMachine bindings
Original patch by Chris Wailes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194143 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 10:25:18 +00:00
Peter Zotov
92198d4f0a [llvm-c] Specify explicit namespace in LLVMLoadLibraryPermanently
Presence of using namespace llvm depended on several #ifdef's, and
this broke the build on mswin32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194142 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 09:45:58 +00:00
Peter Zotov
e669e09d7d [llvm-c] Correctly check for existence of native AsmParser, AsmPrinter, Disassembler
Also, properly name the functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194141 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 09:45:53 +00:00
Peter Zotov
43b255884a [llvm-c] Add functions for initializing native AsmPrinter, AsmParser & Disassembler
Original patch by Chris Wailes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194140 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 09:21:35 +00:00
Peter Zotov
87265f9792 [llvm-c] Expose LLVMLoadLibraryPermanently
Original patch by Chris Wailes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194139 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 09:21:31 +00:00
Peter Zotov
ec7270c966 [OCaml] Impement Llvm_irreader, bindings to LLVM assembly parser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 09:21:25 +00:00
Peter Zotov
c6099db476 [llvm-c] Expose IRReader interface
Original patch by Chris Wailes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194137 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 09:21:15 +00:00
Peter Zotov
ba0c7cd012 [OCaml] Implement Llvm.string_of_llvalue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194136 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 09:21:08 +00:00
Peter Zotov
14bbb1d9b0 [llvm-c] Implement LLVMPrintValueToString
Original patch by Chris Wailes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 09:21:01 +00:00
Reed Kotler
7851bc1871 Fix definition for Mips16 pc relative load word instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194126 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 04:29:52 +00:00
Jiangning Liu
8458f371b8 Implement AArch64 Neon instruction set Perm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 03:35:27 +00:00
Jiangning Liu
258115258f Implement AArch64 Neon instruction set Bitwise Extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 02:25:49 +00:00
Andrew Trick
10bb82e54f Rewrite SCEV's backedge taken count computation.
Patch by Michele Scandale!

Rewrite of the functions used to compute the backedge taken count of a
loop on LT and GT comparisons.

I decided to split the handling of LT and GT cases becasue the trick
"a > b == -a < -b" in some cases prevents the trip count computation
due to the multiplication by -1 on the two operands of the
comparison. This issue comes from the conservative computation of
value range of SCEVs: taking the negative SCEV of an expression that
have a small positive range (e.g. [0,31]), we would have a SCEV with a
fullset as value range.

Indeed, in the new rewritten function I tried to better handle the
maximum backedge taken count computation when MAX/MIN expression are
used to handle the cases where no entry guard is found.

Some test have been modified in order to check the new value correctly
(I manually check them and reasoning on possible overflow the new
values seem correct).

I finally added a new test case related to the multiplication by -1
issue on GT comparisons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194116 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 02:08:26 +00:00
Rafael Espindola
c86cf04650 Remove another unused, and IMHO, not very desirable feature of ErrorOr.
One of the uses of the IsValid flag is to support default constructing
a ErrorOr that is not a Error or a Value. There is not much value in
doing that IMHO. If ErrorOr was to have a default constructor, it
should be implemented by default constructing the value, but even that
looks unnecessary.

The other use is to avoid calling destructors on moved objects. This
looks wrong. If the data being moved has non trivial treatment of
moves (an std::vector for example), it is its destructor that should
handle it, not ~ErrorOr.

With this change ErrorOr becomes a fairly simple wrapper and should
always be better than using an error_code + value in an API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194109 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 23:41:57 +00:00
Reed Kotler
c9080b7bc9 Get rid of current calculation function and adjustment scheme
from MipsConstantIslands. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194108 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 23:36:58 +00:00
Andrew Trick
dc8224def3 Slightly change the way stackmap and patchpoint intrinsics are lowered.
MorphNodeTo is not safe to call during DAG building. It eagerly
deletes dependent DAG nodes which invalidates the NodeMap. We could
expose a safe interface for morphing nodes, but I don't think it's
worth it. Just create a new MachineNode and replaceAllUsesWith.

My understaning of the SD design has been that we want to support
early target opcode selection. That isn't very well supported, but
generally works. It seems reasonable to rely on this feature even if
it isn't widely used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194102 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 22:44:04 +00:00
Reed Kotler
14cfb10174 Get rid of all references to soimm in MipsConstantIslands pass because
we don't have such an operand.
Suprisingly enough, this is never actually accounted for in the 
ARM version when determining offset ranges. In both places there is the
comment:
-    // FIXME: Make use full range of soimm values.
(soimm = shift operand immediate).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194101 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 22:34:29 +00:00
Reed Kotler
1fa282d635 Cleanup getUserOffset. Issues related to inline assembler length and
alignment will be handled differently than in ARM constant islands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194096 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 21:39:57 +00:00
Tim Northover
f635ab8eab ARM: permit bare dmb/dsb/isb aliases on Cortex-M0
Cortex-M0 supports these 32-bit instructions despite being Thumb1 only
(mostly). We knew about that but not that the aliases without the default "sy"
operand were also permitted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194094 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 21:36:02 +00:00
Dmitri Gribenko
5f5095e3dc Convert comments to documentation comments (// -> ///)
Patch by MathOnNapkins


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194093 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 21:28:42 +00:00
Rafael Espindola
af9e8e60ae Use error_code in GVMaterializer.
They just propagate out the bitcode reader error, so we don't need a new enum.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194091 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 19:36:34 +00:00
Jiangning Liu
3ff3a8aa75 Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194085 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 17:42:05 +00:00
Rafael Espindola
e05744ba85 Convert FindFunctionInStream to return an error_code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194084 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 17:16:08 +00:00
Michael Gottesman
f23af8bfd8 [objc-arc] Convert the one directional retain/release relation assert to a conditional check + fail.
Due to the previously added overflow checks, we can have a retain/release
relation that is one directional. This occurs specifically when we run into an
additive overflow causing us to drop state in only one direction. If that
occurs, we should bail and not optimize that retain/release instead of
asserting.

Apologies for the size of the testcase. It is necessary to cause the additive
cfg overflow to trigger.

rdar://15377890

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 16:02:40 +00:00
Alp Toker
04ae34b0aa Provide a test input for opt
This was only working previously due to a quirk in the way lit
concatenates script commands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194078 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 13:57:34 +00:00
Benjamin Kramer
a83342ba3b Silence GCC warning about dropping off a fully covered switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194077 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 13:45:09 +00:00
Peter Zotov
34b4a84261 [OCaml] (PR16190) Add ValueKinds for ConstantDataSequential and subclasses
Original patch by David Monniaux

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194075 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 12:55:43 +00:00
Peter Zotov
0fac3dfa41 [llvm-c] (PR16190) Add LLVMIsA* functions for ConstantDataSequential and subclasses
Original patch by David Monniaux

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194074 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 12:55:37 +00:00
Peter Zotov
225146951e [OCaml] (PR10016) Add a few missing line in OCamlLangImpl2.rst
Original patch by Damien Schoof

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 12:14:04 +00:00
Reed Kotler
a2e6e6bcf8 Remove the word "thumb" from comments. Remove also an incorrect
command regarding the porting from the ARM version (was an old comment).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194066 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 12:04:37 +00:00
Peter Zotov
c8ac229cc8 [OCaml] (PR16318) Add missing argument to Llvm.const_intcast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194065 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 11:56:20 +00:00
Peter Zotov
150c95eab5 [OCaml] (PR11717) Make declare_qualified_global respect address argument
Original patch by Jonathan Ragan-Kelley

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194064 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 11:56:13 +00:00
David Majnemer
8f198b0d60 X86 Disassembler: remove unused bool typedef-name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194062 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 10:34:42 +00:00
Alp Toker
4d6b695c95 Suppress OS crash dialog in llvm-rtdyld
All other tools have this -- it's needed to avoid hanging lit on Windows in
case of a crash.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194060 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 09:33:43 +00:00
Peter Zotov
19648c00d6 [OCaml] Properly tag the custom operations of Llvm.llbuilder
All other custom operations tags have LLVM prefix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194058 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 09:13:46 +00:00
Peter Zotov
9a62ec7308 [OCaml] Llvm_linker: do not use external in module interface
Workaround for an OCaml bug:
http://caml.inria.fr/mantis/view.php?id=4166

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194057 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 09:13:39 +00:00
Reed Kotler
c0e9800d45 Fix r194019 as requested by Eric Christopher.
Submit the basic port of the rest of ARM constant islands code to Mips. 
Two test cases are added which reflect the next level of functionality:
constants getting moved to water areas that are out of range from the
initial placement at the end of the function and basic blocks being split to
create water when none exists that can be used. There is a bunch of this
code that is not complete and has been marked with IN_PROGRESS. I will
finish cleaning this all up during the next week or two and submit the
rest of the test cases. I have elminated some code for dealing with
inline assembly because to me it unecessarily complicates things and
some of the newer features of llvm like function attributies and builtin
assembler give me better tools to solve the alignment issues created
there. Also, for Mips16 I even have the option of not doing constant
islands in the present of inline assembler if I chose. When everything
has been completed I will summarize the port and notify people that
are knowledgable regarding the ARM Constant Islands code so they can
review it in it's entirety if they wish.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194053 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 08:14:14 +00:00
Alp Toker
ddfc20dea4 Fix symbol defines in config.h.cmake
These were incorrectly pointing to HAVE_LOG despite being checked for
correctly in config-ix.cmake.

Patch by James Lyon!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194051 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 07:27:18 +00:00
Craig Topper
f6157f00db Lift alignment restrictions on load folding for a significant portion of AVX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194048 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 06:31:43 +00:00
Hao Liu
591c2f738a Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post).
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194043 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 03:39:32 +00:00
Kevin Qin
8263dcdf23 Implemented aarch64 neon intrinsic vcopy_lane with float type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194041 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 02:03:59 +00:00