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11372 Commits

Author SHA1 Message Date
Bill Wendling
2f46f1f59c Add encoding for VSTR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118220 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 00:59:42 +00:00
Owen Anderson
60f4870c22 Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization. 
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 23:15:26 +00:00
Owen Anderson
d966817f3c Add support for code generation of the one register with immediate form of vorr. 
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 22:44:51 +00:00
Evan Cheng
949c910fb3 Fix test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118187 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 18:21:33 +00:00
Owen Anderson
7a25825033 Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead, 
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118183 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 18:16:27 +00:00
Dale Johannesen
d5ce456161 This test assumes SSE is present; that is not the default 
on non-X86 hosts.  Hopefully fixes ppc-host buildbot.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118182 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 18:08:41 +00:00
Bob Wilson
d168cef664 Add codegen patterns for VST1-lane instructions. Radar 8599955. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118176 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 16:24:53 +00:00
Bob Wilson
3468c2ee20 Check for extractelement with a variable operand for the element number. 
For NEON we had been assuming this was always an immediate constant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118175 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 16:24:50 +00:00
Evan Cheng
dfed19fe2c Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 06:34:55 +00:00
Evan Cheng
bc7deb0f75 Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 05:14:24 +00:00
Bill Wendling
92b5a2eb16 The MC code couldn't handle ARM LDR instructions with negative offsets: 
vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 01:49:29 +00:00
Dan Gohman
394d6298bc Fix DAGCombiner to avoid going into an infinite loop when it 
encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff).
This fixes rdar://8606584.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118143 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 01:47:46 +00:00
Evan Cheng
8239daf7c8 Two sets of changes. Sorry they are intermingled. 
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
   "optimize for latency". Call instructions don't have the right latency and
   this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
   not # of micro-ops since multi-latency instructions is completely executed
   even when the predicate is false. Also, some instruction will be "slower"
   when they are predicated due to the register def becoming implicit input.
   rdar://8598427


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 00:45:17 +00:00
Chris Lattner
f4b284f991 chase owen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118124 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 23:55:24 +00:00
Chris Lattner
ca99597ed5 tweak this to pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118122 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 23:50:17 +00:00
Chris Lattner
d5b02302f3 temporarily xfail this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118120 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 23:44:50 +00:00
John Thompson
45c21ff044 Inline asm mult-alt constraint tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118107 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 23:01:44 +00:00
Bill Wendling
5df0e0a61d Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work 
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 22:31:46 +00:00
Owen Anderson
b20594fce6 Provide correct encodings for the remaining vst variants that we currently generate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118087 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 22:18:18 +00:00
Owen Anderson
a1a45fd254 Add correct encodings for basic variants for vst3 and vst4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118082 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 21:47:03 +00:00
Owen Anderson
d2f3794e4d Add correct encodings for the basic variants for vst2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118068 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 21:16:58 +00:00
Owen Anderson
cfebe3a8b1 Add correct encodings for the basic form of vst1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118067 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 21:06:06 +00:00
Owen Anderson
f0ea0f2b15 Add correct encodings for the rest of the vld instructions that we generate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118053 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 20:40:59 +00:00
Jim Grosbach
ab3d00e535 Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke 
assumptions about stack layout. Specifically, LR must be saved next to FP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118026 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 17:35:25 +00:00
Rafael Espindola
3ff57094a7 Add support for expressions in .sleb/.uleb directives. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118023 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 17:22:24 +00:00
Devang Patel
a90b305af9 Use frameindex, if available, as a last resort to emit debug info for a parameter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118020 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 17:01:30 +00:00
Owen Anderson
cf667be17b Add correct NEON encodings for vld2, vld3, and vld4 basic variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117997 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 01:24:55 +00:00
Owen Anderson
d9aa7d30aa Add correct NEON encodings for the "multiple single elements" form of vld. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 00:05:05 +00:00
Bob Wilson
665814b6be Add support for alignment operands on VLD1-lane instructions. 
This is another part of the fix for Radar 8599955.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117976 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 23:40:51 +00:00
Bob Wilson
baf0615426 Add VLD1-lane testcases for quad-register types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117975 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 23:40:46 +00:00
Bob Wilson
b796bbb6de Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117964 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 22:04:05 +00:00
Bill Wendling
933b314c76 Use ARM-style comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 21:16:39 +00:00
Owen Anderson
648b20d5db When folding away a (shl (shr)) pair, we need to check that the bits that will BECOME the low 
bits are zero, not that the current low bits are zero.  Fixes <rdar://problem/8606771>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117953 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 21:08:20 +00:00
Bill Wendling
40a5eb18b0 When we look at instructions to convert to setting the 's' flag, we need to look 
at more than those which define CPSR. You can have this situation:

(1)  subs  ...
(2)  sub   r6, r5, r4
(3)  movge ...
(4)  cmp   r6, 0
(5)  movge ...

We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:

(1)  sub   r1, r2, r3
(2)  sub   r4, r5, r6
(3)  cmp   r4, ...
(5)  movge ...
(6)  cmp   r1, ...
(7)  movge ...

We cannot convert (1) to "subs" because of the intervening use of CPSR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 20:41:43 +00:00
Owen Anderson
95b9766fea Use ARM-style comment syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117941 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 18:33:37 +00:00
Bob Wilson
24645a1a6d NEON does not support truncating vector stores. Radar 8598391. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117940 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 18:31:39 +00:00
Owen Anderson
4845f99008 Covert this test to .s form. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117939 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 18:30:39 +00:00
Owen Anderson
60b75fad7e Convert this test to .s form. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117938 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 18:26:43 +00:00
Owen Anderson
3b5dfcd8fd Covert this test to .s form. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117937 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 18:13:11 +00:00
Owen Anderson
2bcb989a0b Covert this test to .s form. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117935 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 18:03:16 +00:00
Rafael Espindola
d1d73b03af Fix test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117932 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 17:10:53 +00:00
Rafael Espindola
c70a1d985a Write the line info to .debug_line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117930 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 17:07:14 +00:00
Jim Grosbach
833c93c795 Mark ARM subtarget features that are available for the assembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117929 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 16:59:54 +00:00
Rafael Espindola
cc3acee7b3 Add support for .value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117922 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 15:29:07 +00:00
Rafael Espindola
484291c273 Implement .weakref. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117911 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 14:28:48 +00:00
Bill Wendling
504fb4fb8e More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when the 
peephole optimizer is disabled. That's not good at all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117905 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 05:59:43 +00:00
Bill Wendling
59707e8055 Disable because peephole is disabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117903 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 05:48:44 +00:00
Chris Lattner
acc473fcf9 "mov[zs]x (mem), GR16" are not ambiguous: the mem 
must be 8 bits.  Support this memory form.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117902 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 05:41:10 +00:00
Chris Lattner
b501d4f673 Implement enough of the missing instalias support to get 
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117901 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 05:34:34 +00:00
Owen Anderson
b8d14a6611 Convert this test to .s form. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117900 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 05:23:58 +00:00