Commit Graph

104490 Commits

Author SHA1 Message Date
Rafael Espindola
c3c6d5fcb8 Use an enum class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210620 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 01:09:09 +00:00
Eric Christopher
f68129838b Remove duplicate copy of InstrItineraryData from the TargetMachine,
it's already on the subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210619 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 00:53:17 +00:00
Eric Christopher
e290e4abc3 Move to a private function to initialize the subtarget dependencies
so that we can use initializer lists for the AArch64 Subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210616 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 00:46:34 +00:00
Eric Christopher
0166af890c Move to a private function to initialize the subtarget dependencies
so that we can use initializer lists for the X86Subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210614 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 00:25:19 +00:00
Eric Christopher
75408c8f80 Sort includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210613 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 00:25:16 +00:00
Juergen Ributzka
0adbcf3ba9 [FastISel][X86] Extend support for {s|u}{add|sub|mul}.with.overflow intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210610 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 23:52:44 +00:00
Eric Christopher
9c84db6ba3 Use unique_ptr for X86Subtarget pointer members.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210606 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 23:26:47 +00:00
Eric Christopher
fe80185273 Move AArch64TargetLowering to AArch64Subtarget.
This currently necessitates a TargetMachine for the TargetLowering
constructor and TLOF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210605 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 23:26:45 +00:00
Zachary Turner
63ce00b72f Revert "Remove support for runtime multi-threading."
This reverts revision r210600.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210603 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 23:15:43 +00:00
Zachary Turner
529e9d307e Remove support for runtime multi-threading.
This patch removes the functions llvm_start_multithreaded() and
llvm_stop_multithreaded(), and changes llvm_is_multithreaded()
to return a constant value based on the value of the compile-time
definition LLVM_ENABLE_THREADS.

Previously, it was possible to have compile-time support for
threads on, and runtime support for threads off, in which case
certain mutexes were not allocated or ever acquired.  Now, if the
build is created with threads enabled, mutexes are always acquired.

A test before/after patch of compiling a very large TU showed no
noticeable performance impact of this change.

Reviewers: rnk

Differential Revision: http://reviews.llvm.org/D4076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210600 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 23:01:20 +00:00
Eric Christopher
159e408563 Move AArch64InstrInfo to AArch64Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210599 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 22:57:25 +00:00
Eric Christopher
468a0ce16f Remove a method that was just replacing direct access to a member.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210598 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 22:57:21 +00:00
Hans Wennborg
a327ac3e51 lit: warn when passed invalid pathname
It would previously say things like

  warning: input 'test/Frontend/foo.c' contained no tests

and have the user pull their hair trying to figure out what's wrong with that
file. This patch changes the message to the much clearer:

  warning: no such file or directory: 'test/Frontend/foo.c'

Differential Revision: http://reviews.llvm.org/D4097

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210597 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 22:51:58 +00:00
Eric Christopher
c6e5ff46be Remove the use of TargetMachine from X86InstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210596 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 22:34:31 +00:00
Eric Christopher
c72fe200ad Move X86RegisterInfo away from using the TargetMachine and only
using the subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210595 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 22:34:28 +00:00
Rafael Espindola
fbb5f70186 Mark a few functions noexcept.
This reduces the difference between std::error_code and llvm::error_code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210591 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 21:26:47 +00:00
Eric Christopher
f85ae2a8c2 Use the TargetMachine on the DAG or the MachineFunction instead
of using the cached TargetMachine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210589 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 21:25:13 +00:00
Tom Stellard
cd0b8d6cbf R600/SI: Emit an error when attempting to spill VGPRs v4
I can't get VGPR spilling to work reliable, so for now just emit
an error when the register allocator tries to spill VGPRs.

v2:
  - Fix build
v3:
  - Added crash fix when spilling SPGRs
v4:
  - Use V_MOV_B32 as a dummy instruction instead of S_NOP

Patch by: Darren Powell

https://bugs.freedesktop.org/show_bug.cgi?id=75276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210588 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 21:20:41 +00:00
Tom Stellard
48d11b0228 R600/SI: Fix a crash when spilling SGPRs
We need to make sure only one new instruction is added when spilling
otherwise the register allocator may crash.

This fixes a crash in the game Antichamber.

https://bugs.freedesktop.org/show_bug.cgi?id=75276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210587 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 21:20:38 +00:00
Rafael Espindola
40b0a148a2 Add a LLVM_NOEXCEPT to Compiler.h.
This will be needed for the switch to std::error_code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210581 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 20:45:52 +00:00
Eric Christopher
387fe1eff4 We already have a reference to the TargetMachine, use that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210580 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 20:39:39 +00:00
Eric Christopher
ad3aa5eb5a Have isInTailCallPosition take the DAG so that we can use the
version of TargetLowering/Machine from there on the way to avoiding
TargetMachine in TargetLowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210579 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 20:39:38 +00:00
Eric Christopher
4d9df32652 Reorder includes to be sorted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210578 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 20:39:35 +00:00
Reid Kleckner
733073df6a Rearrange the CHECK lines in this test to make failure more obvious.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210575 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 20:16:47 +00:00
Reid Kleckner
e21498e604 Revert "Patch by Ray Donnelly to print register names instead of numbers."
This reverts commit r206683.

The code was confusing SEH register numbers with DWARF register numbers.
The test case it was committed with was obviously incorrect.  The
disassembler was roundtripping '.seh_pushreg %rsi' as '.seh_pushreg
%rbp', and other exciting things.

Noticed by Vadim Chugunov.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210574 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 20:16:36 +00:00
Matt Arsenault
258e8223e6 Fix error in tablegen when either operand of !if is an empty list.
!if([Something], []) would error with "No type for list".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210572 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 20:10:08 +00:00
Eric Christopher
1916157ef6 Fix typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210571 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 20:07:29 +00:00
Matt Arsenault
1f4772305a R600: Use BCNT_INT for evergreen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210569 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 19:18:28 +00:00
Matt Arsenault
69891c0115 R600/SI: Implement i64 ctpop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210568 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 19:18:24 +00:00
Matt Arsenault
ee9772d9dd R600/SI: Use bcnt instruction for ctpop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210567 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 19:18:21 +00:00
Rafael Espindola
81ff9cdedb Use an enum class now that they are available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210566 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 19:08:21 +00:00
Matt Arsenault
bfd00e21b7 R600: Handle fcopysign
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210564 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 19:00:20 +00:00
Matt Arsenault
0ba78a9121 R600/SI: Handle sign_extend and zero_extend to i64 with patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210563 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 18:54:59 +00:00
Eric Christopher
a1c71aa78d Add a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210559 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 18:31:18 +00:00
Eric Christopher
30ad4cb09b Move AArch64SelectionDAGInfo down to the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210557 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 18:21:53 +00:00
Juergen Ributzka
7d1e002914 [FastISel] Collect statistics about failing intrinsic calls.
Add more instruction-specific statistics about failing intrinsic calls during
FastISel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210556 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 18:17:00 +00:00
Eric Christopher
75b55475bc Remove the cached little endian variable. We can get it easily off
of the DataLayout.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210555 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 18:11:20 +00:00
Eric Christopher
b8dca33a05 Have AArch64SelectionDAGInfo take a DataLayout parameter rather
than a TargetMachine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210554 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 18:06:28 +00:00
Eric Christopher
e3a06bcd8a Remove caching of the subtarget for AArch64SelectionDAGInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210553 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 18:06:25 +00:00
Eric Christopher
fc0f6e8cc5 Move DataLayout onto the AArch64 subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210552 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 18:06:23 +00:00
Zachary Turner
9a7d793fd1 Test commit, wraps some lines to fit in 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210551 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 18:03:04 +00:00
Eric Christopher
c4f9370391 Move AArch64FrameLowering into the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210549 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 17:44:12 +00:00
Eric Christopher
8128a7965f Remove the uses of AArch64TargetMachine and AArch64Subtarget from
AArch64FrameLowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210548 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 17:33:39 +00:00
Reed Kotler
805c9e4943 Do Materialize Floating Point in Mips Fast-Isel
Summary:
Implement materialize of floating point literals in Mips Fast-Isel

Reopened version of D3659

Test Plan: simplestorefp1.ll

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D4071

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210546 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 16:45:44 +00:00
Andrea Di Biagio
c0edcf7de8 [X86] Improved target combine rules for selecting horizontal add/sub.
This patch slightly changes the algorithm introduced at revision 210477
to fix a problem where the algorithm was producing incorrect code for 
the VEX.256 encoded versions of horizontal add/sub.

For these cases, we now try to split the two 256-bit vectors into
128-bit chunks before emitting horizontal add/sub dag nodes.

Added a new test case into haddsub-2.ll.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210545 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 16:42:57 +00:00
Tom Stellard
7dd65e6cee Hexagon: Expand i1 SELECT_CC
il is legal for Hexagon, so I should have marked this as Expand for
SELECT_CC when I removed setOperationAction(ISD::SELECT_CC, MVT::Other,
Expand); in r210541.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210544 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 16:42:41 +00:00
Adam Nemet
8dea1c4167 [X86] AVX512: Add vmovntdqa
Along with the corresponding intrinsic and tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210543 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 16:39:53 +00:00
Renato Golin
2d89932fb2 Fix a bug in the Thumb1 ARM Load/Store optimizer
Previously, the basic block was searched for future uses of the base register,
and if necessary any writeback to the base register was reset using a SUB
instruction (e.g. before calling a function) just before such a use. However,
this step happened *before* the merged LDM/STM instruction was built. So if
there was (e.g.) a function call directly after the not-yet-formed LDM/STM,
the pass would first insert a SUB instruction to reset the base register,
and then (at the same location, incorrectly) insert the LDM/STM itself.

This patch fixes PR19972. Patch by Moritz Roth.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210542 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 16:39:21 +00:00
Tom Stellard
102d0f3e3f SelectionDAG: Don't use MVT::Other to determine legality of ISD::SELECT_CC
The SelectionDAG bad a special case for ISD::SELECT_CC, where it would
allow targets to specify:

setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);

to indicate that they wanted to expand ISD::SELECT_CC for all types.
This wasn't applied correctly everywhere, and it makes writing new
DAG patterns with ISD::SELECT_CC difficult.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210541 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 16:01:29 +00:00
Tom Stellard
c23f0e1e44 SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, y)) for vectors
This prevents a future commit from regressing:

test/CodeGen/R600/setcc-equivalent.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210540 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 16:01:25 +00:00