Commit Graph

82819 Commits

Author SHA1 Message Date
Rafael Espindola
c49b29ef5d Require intervals in the range metadata to be in a canonical form: They must
be non contiguous, non overlapping and sorted by the lower end.

While this is technically a backward incompatibility, every frontent currently
produces range metadata with a single interval and we don't have any pass
that merges intervals yet, so no existing bitcode files should be rejected by
this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157741 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31 13:45:46 +00:00
Elena Demikhovsky
177cf1e1a3 Added FMA3 Intel instructions.
I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks.
I added tests for GodeGen and intrinsics.
I did not change llvm.fma.f32/64 - it may be done later.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31 09:20:20 +00:00
Duncan Sands
53b4177df7 Enhance the sinking code to handle diamond patterns. Patch by
Carlo Alberto Ferraris.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157736 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31 08:09:49 +00:00
Craig Topper
0559a2f8ae Add intrinsic for pclmulqdq instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157731 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31 04:37:40 +00:00
Akira Hatanaka
28ee4fdf20 Cleanup and factoring of mips16 tablegen classes. Make register classes
CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.

Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157730 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31 02:59:44 +00:00
Eric Christopher
feba19309d Fix typo in assembly directive. Noticed by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157726 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31 00:53:18 +00:00
Akira Hatanaka
f6a186ed0b Add lit.local.cfg to run the tests in test/MC/Disassembler/Mips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157725 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31 00:49:56 +00:00
Jakob Stoklund Olesen
4c91bdafac Avoid depending on list orders and register numbering.
This code is covered by test/CodeGen/ARM/arm-modifier.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157720 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 23:00:43 +00:00
Jakob Stoklund Olesen
4aecc761c7 Extract some pointer hacking to a function.
Switch to MCSuperRegIterator while we're there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157717 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 22:40:03 +00:00
Jakob Stoklund Olesen
9cda1be0aa Prioritize smaller register classes for urgent evictions.
It helps compile exotic inline asm. In the test case, normal GR32
virtual registers use up eax-edx so the final GR32_ABCD live range has
no registers left. Since all the live ranges were tiny, we had no way of
prioritizing the smaller register class.

This patch allows tiny unspillable live ranges to be evicted by tiny
unspillable live ranges from a smaller register class.

<rdar://problem/11542429>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157715 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 21:46:58 +00:00
Jakob Stoklund Olesen
ff09e56cda Print uint16_t numbers without a sign.
It seems I broke C++11.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157711 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 19:20:19 +00:00
Eric Christopher
6ab75b4dcb Add support for the mips inline asm 'm' output modifier.
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157709 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 19:05:19 +00:00
Owen Anderson
f917d20561 Switch the canonical FMA term operand order to match both the comment I wrote and the usual LLVM convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157708 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 18:54:50 +00:00
Owen Anderson
85ef6f4c99 Teach DAGCombine to canonicalize the position of a constant in the term operands of an FMA node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157707 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 18:50:39 +00:00
Chad Rosier
06a23ea808 Remove extra space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157706 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 18:47:55 +00:00
David Blaikie
4f56a30e0d Reinstate -O3 for LTO.
This broke in r144788 when the CodeGenOpt option was moved from everywhere else
(specifically, from addPassesToEmitFile) to createTargetMachine. Since
LTOCodeGenerator wasn't passing the 4th argument, when the 4th parameter became
the 3rd, it silently continued to compile (int->bool conversion) but meant
something completely different.

This change preserves the existing (accidental) and previous (default)
semantics of the addPassesToEmitFile and restores the previous/intended
CodeGenOpt argument by passing it appropriately to createTargetMachine.

(discovered by pending changes to -Wconversion to catch constant->bool
conversions)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157705 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 18:42:51 +00:00
Benjamin Kramer
127563b216 Make sure that we're dealing with a binary SCEVExpr when simplifying.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157704 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 18:42:43 +00:00
Jakob Stoklund Olesen
6c823822cd Fix some uses of getSubRegisters() to use getSubReg() instead.
It is better to address sub-registers directly by name instead of
relying on their position in the sub-register list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157703 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 18:40:49 +00:00
Jakob Stoklund Olesen
275fd2523e Remove some redundant tests.
An empty list is not represented as a null pointer. Let TRI do its own
shortcuts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157702 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 18:38:56 +00:00
Benjamin Kramer
6cf07a80ff Teach SCEV's icmp simplification logic that a-b == 0 is equivalent to a == b.
This also required making recursive simplifications until
nothing changes or a hard limit (currently 3) is hit.

With the simplification in place indvars can canonicalize
loops of the form
for (unsigned i = 0; i < a-b; ++i)
into
for (unsigned i = 0; i != a-b; ++i)
which used to fail because SCEV created a weird umax expr
for the backedge taken count.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157701 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 18:32:23 +00:00
Chris Lattner
f186df0d3e it's pointed out that R11 can be used for magic things, and doing things just for 64-bit registers is silly. Just optimize 3 more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157699 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 18:08:02 +00:00
Chris Lattner
5aaabbfe62 Extend the (abi-irrelevant) return convention to be able to return more than two values in
integer registers.  This is already supported by the fastcc convention, but it doesn't
hurt to support it in the standard conventions as well.

In cases where we can cheat at the calling convention, this allows us to avoid returning
things through memory in more cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157698 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 17:50:14 +00:00
Chad Rosier
ada759d5fa [arm-fast-isel] Add support for the llvm.frameaddress() intrinsic.
Patch by Jush Lu <jush.msn@gmail.com>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157696 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 17:23:22 +00:00
Jakob Stoklund Olesen
cd00ef033c Add MCRegisterInfo::RegListIterator.
Also add subclasses MCSubRegIterator, MCSuperRegIterator, and
MCRegAliasIterator.

These iterators provide an abstract interface to the MCRegisterInfo
register lists so the internal representation can be changed without
changing all clients.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157695 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 16:36:28 +00:00
Benjamin Kramer
1afbd278d1 Mark insertq/extrq intrinsic readnone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157688 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 13:44:25 +00:00
Benjamin Kramer
77fc4b297a Port support for SSE4a extrq/insertq to the old jit code emitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157685 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 09:13:55 +00:00
Benjamin Kramer
dee3be6029 Remove little semicolon that caused a lot of warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157684 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 09:13:49 +00:00
Kostya Serebryany
e6cf2e0bd0 [asan] instrument cmpxchg and atomicrmw
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157683 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 09:04:06 +00:00
Andrew Trick
fe3516f9a5 SCEV: Handle a corner case reducing AddRecExpr * AddRecExpr
If integer overflow causes one of the terms to reach zero, that can
force the entire expression to zero.

Fixes PR12929: cast<Ty>() argument of incompatible type

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157673 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 03:35:20 +00:00
Andrew Trick
97178aedb5 Reformat the loop that does AddRecExpr * AddRecExpr reduction.
No functionality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157672 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 03:35:17 +00:00
Evan Cheng
eb25bd2356 Teach taildup to update livein set. rdar://11538365
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157663 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 00:42:39 +00:00
Evan Cheng
3d4166dff0 If-converter models predicated defs as read + write. The read should be marked as 'undef' since it may not already be live. This appeases -verify-machineinstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157662 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 00:42:02 +00:00
Chris Lattner
ef09705ee5 typo fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157661 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 00:40:23 +00:00
Bob Wilson
6e1b812850 Add an insertPass API to TargetPassConfig. <rdar://problem/11498613>
Besides adding the new insertPass function, this patch uses it to
enhance the existing -print-machineinstrs so that the MachineInstrs
after a specific pass can be printed.

Patch by Bin Zeng!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 00:17:12 +00:00
Jakob Stoklund Olesen
209cdc2999 Make DiffListIterator public to unbreak the gcc buildbots.
Apparently, a friend can't derive from a private class according to gcc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 00:05:03 +00:00
Jakob Stoklund Olesen
96feada378 Use MCRegUnitIterator to compute regsOverlap().
The register unit lists are typically much shorter than the register
overlap lists, and the backing table for register units has better cache
locality because it is smaller.

This makes llc about 0.5% faster. The regsOverlap() function isn't that hot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157651 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29 23:40:02 +00:00
Jakob Stoklund Olesen
f52baf72c1 Emit register unit lists for each register.
Register units are already used internally in TableGen to compute
register pressure sets and overlapping registers. This patch makes them
available to the code generators.

The register unit lists are differentially encoded so they can be reused
for many related registers. This keeps the total size of the lists below
200 bytes for most targets. ARM has the largest table at 560 bytes.

Add an MCRegUnitIterator for traversing the register unit lists. It
provides an abstract interface so the representation can be changed in
the future without changing all clients.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157650 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29 23:40:00 +00:00
Nuno Lopes
988a089164 bounds checking:
- hoist checks out of loops where SCEV is smart enough
 - add additional statistics to measure how much we loose for not supporting interprocedural and pointers loaded from memory

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29 22:32:51 +00:00
Douglas Gregor
aad8296383 DenseMap's move assignment operator needs to return *this
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157644 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29 20:33:09 +00:00
Evan Cheng
cac58aa80e Optional def can be either a def or a use (of reg0).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157640 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29 19:40:44 +00:00
Benjamin Kramer
1386e9b7b1 Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29 19:05:25 +00:00
Lang Hames
f905f69668 Clear the entering, exiting and internal ranges of a bundle before collecting
ranges for the instruction about to be bundled. This fixes a bug in an external
project where an assertion was triggered due to spurious 'multiple defs' within
the bundle.

Patch by Ivan Llopard. Thanks Ivan!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29 18:19:54 +00:00
Nicolas Geoffray
e23642916b Update CPPBackend to new API for AttrListPtr::get.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157624 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29 15:07:18 +00:00
Stepan Dyatkovskiy
0aa32d5d0f ConstantRangesSet renamed to IntegersSubset. CRSBuilder renamed to IntegersSubsetMapping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157612 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29 12:26:47 +00:00
Peter Collingbourne
b34d3aa35b Add llvm.fabs intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157594 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-28 21:48:37 +00:00
Benjamin Kramer
7bb9f063be Fix suspicous hasOneUse() check, found by PVS Studio (PR12357).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157592 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-28 20:52:48 +00:00
Benjamin Kramer
37fa1c81ac InstCombine: Fix infinite loop when encountering switch on trivial icmp.
The test case feeds the following into InstCombine's visitSelect:
%tobool8 = icmp ne i32 0, 0
%phitmp = select i1 %tobool8, i32 3, i32 0
Then instcombine replaces the right side of the switch with 0, doesn't notice
that nothing changes and tries again indefinitely.

This fixes PR12897.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157587 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-28 19:18:16 +00:00
David Blaikie
21280e48c0 Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157586 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-28 18:23:36 +00:00
Meador Inge
e99f8be067 PR12696: Attribute bits above 1<<30 are not encoded in bitcode
Attribute bits above 1<<30 are now encoded correctly.  Additionally,
the encoding/decoding functionality has been hoisted to helper functions
in Attributes.h in an effort to help the encoding/decoding to stay in
sync with the Attribute bitcode definitions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157581 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-28 15:45:43 +00:00
Benjamin Kramer
f52aea8bc2 Random BitcodeReader cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157577 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-28 14:10:31 +00:00