the TableGen descriptions; all unset bits are thus errors.
* As a result, found and fixed instructions where some operands were not
actually assigned into the right portion of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7074 91177308-0d34-0410-b5e6-96231b3b80d8
* Added instruction classes which start building from rs1, then rs2, and rd.
* Fixed order of operands in classes 4.1 and 4.2; added 4.6 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6561 91177308-0d34-0410-b5e6-96231b3b80d8
SparcInstrSelection.cpp:
* Fixed opcodes to return correct 'i' version since the two functions are each
only used in one place.
* Changed name of function to have an 'i' in the name to signify that they each
return an immediate form of the opcode.
* Added a warning if either of the functions is ever used in a context which
requires a register-version opcode.
SparcV9_F4.td: fixed class F4_3, added F4_4 and notes that F4_{1,2} need fixing
SparcV9.td: added the MOV(F)cc instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6548 91177308-0d34-0410-b5e6-96231b3b80d8
* Added some Format 4 classes, but not instructions
* Added notes on missing sections with FIXMEs
* Added RDCCR instr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6388 91177308-0d34-0410-b5e6-96231b3b80d8
