Commit Graph

286 Commits

Author SHA1 Message Date
Gabor Greif
04ac81d5db Move the search for the appropriate AND instruction
into OptimizeCompareInstr.
This necessitates the passing of CmpValue around,
so widen the virtual functions to accomodate.

No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114428 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 12:01:15 +00:00
Bill Wendling
a65568676d Rename ConvertToSetZeroFlag to something more general.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113670 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-11 00:13:50 +00:00
Bill Wendling
3665661a57 No need to recompute the SrcReg and CmpValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113666 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 23:46:12 +00:00
Bill Wendling
92ad57f066 Move some of the decision logic for converting an instruction into one that sets
the 'zero' bit down into the back-end. There are other cases where this logic
isn't sufficient, so they should be handled separately.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113665 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 23:34:19 +00:00
Bill Wendling
220e240bdf Modify the comparison optimizations in the peephole optimizer to update the
iterator when an optimization took place. This allows us to do more insane
things with the code than just remove an instruction or two.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 21:55:43 +00:00
Evan Cheng
3ef1c8759a Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 01:29:16 +00:00
Evan Cheng
5f54ce3473 For each instruction itinerary class, specify the number of micro-ops each
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.

This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 18:18:55 +00:00
Bill Wendling
c98af3370f Use the "isCompare" machine instruction attribute instead of calling the
relatively expensive comparison analyzer on each instruction. Also rename the
comparison analyzer method to something more in line with what it actually does.

This pass is will eventually be folded into the Machine CSE pass.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110539 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-08 05:04:59 +00:00
Bill Wendling
e4ddbdfd3c Add the Optimize Compares pass (disabled by default).
This pass tries to remove comparison instructions when possible. For instance,
if you have this code:

   sub r1, 1
   cmp r1, 0
   bz  L1

and "sub" either sets the same flag as the "cmp" instruction or could be
converted to set the same flag, then we can eliminate the "cmp" instruction all
together. This is a important for ARM where the ALU instructions could set the
CPSR flag, but need a special suffix ('s') to do so.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110423 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06 01:32:48 +00:00
Chris Lattner
2062875a7d eliminate the TargetInstrInfo::GetInstSizeInBytes hook.
ARM/PPC/MSP430-specific code (which are the only targets that
implement the hook) can directly reference their target-specific
instrinfo classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109171 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 21:27:00 +00:00
Chris Lattner
134d8eec87 remove the JIT "NeedsExactSize" feature and supporting logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 21:17:55 +00:00
Jakob Stoklund Olesen
78e6e00922 Remove the isMoveInstr() hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 22:35:46 +00:00
Jakob Stoklund Olesen
af462c4b4f Remove remaining calls to TII::isMoveInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108556 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 21:03:55 +00:00
Eric Christopher
5a3eb8f0e1 80-col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108420 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-15 07:49:30 +00:00
Jakob Stoklund Olesen
744b3a5acd Remove TargetInstrInfo::copyRegToReg entirely.
Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no
longer a default implementation forwarding to copyRegToReg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108095 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 17:01:17 +00:00
Jakob Stoklund Olesen
b0a258be2f Remove copyRegToReg from TargetInstrInfo so it is not longer accesible.
Use a COPY instruction instead for register copies, or TII::copyPhysReg() after
COPY instructions are lowered.

Targets should implement copyPhysReg instead of copyRegToReg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108075 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 05:17:06 +00:00
Jakob Stoklund Olesen
1f32340d95 Automatically fold COPY instructions into stack load/store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108012 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 20:43:13 +00:00
Jakob Stoklund Olesen
e05442d508 Change TII::foldMemoryOperand API to require the machine instruction to be
inserted in a MBB, and return an already inserted MI.

This target API change is necessary to allow foldMemoryOperand to call
storeToStackSlot and loadFromStackSlot when folding a COPY to a stack slot
reference in a target independent way.

The foldMemoryOperandImpl hook is going to change in the same way, but I'll wait
until COPY folding is actually implemented. Most targets only fold copies and
won't need to specialize this hook at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 17:29:08 +00:00
Jakob Stoklund Olesen
0bc25f4040 Convert EXTRACT_SUBREG to COPY when emitting machine instrs.
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.

Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 16:40:22 +00:00
Jakob Stoklund Olesen
3651d92d91 Add TargetInstrInfo::copyPhysReg hook and use it from LowerSubregs.
This target hook is intended to replace copyRegToReg entirely, but for now it
calls copyRegToReg.

Any remaining calls to copyRegToReg wil be replaced by COPY instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 05:01:41 +00:00
Evan Cheng
13151432ed Change if-conversion block size limit checks to add some flexibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 22:42:03 +00:00
Bob Wilson
f0e1b89421 Edit and clarify comments for TargetInstrInfo methods:
None of the existing implementations of commuteInstruction create new
instructions unless the NewMI parameter is true, but the comment had
implied otherwise.

findCommutedOpIndices returns false, not true, when it doesn't know
how to commute the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 16:48:26 +00:00
Evan Cheng
4d54e5b2dd Tail merging pass shall not break up IT blocks. rdar://8115404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106517 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 01:18:16 +00:00
Evan Cheng
86050dc8cc Allow ARM if-converter to be run after post allocation scheduling.
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:09:54 +00:00
Stuart Hastings
3bf9125933 Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 22:43:56 +00:00
Evan Cheng
729aab3dd3 Allow target to provide its own hazard recognizer to post-ra scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105862 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 00:12:18 +00:00
Evan Cheng
68fc2daf8f Allow target to place 2-address pass inserted copies in better spots. Thumb2 will use this to try to avoid breaking up IT blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09 19:26:01 +00:00
Jakob Stoklund Olesen
9edf7deb37 Slightly change the meaning of the reMaterialize target hook when the original
instruction defines subregisters.

Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.

Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:

  %reg1234:foo = FLAP %reg1234<imp-def>

will reMaterialize(%reg3333, bar) like this:

  %reg3333:bar-foo = FLAP %reg333:bar<imp-def>

Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 22:47:25 +00:00
Evan Cheng
2457f2c661 Implement @llvm.returnaddress. rdar://8015977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 01:47:14 +00:00
Dan Gohman
34dcc6fadc Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:33:48 +00:00
Evan Cheng
746ad69e08 Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 19:06:44 +00:00
Evan Cheng
8601a3d4de Frame index can be negative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-29 01:13:30 +00:00
Chris Lattner
ee9eb411ff on darwin empty functions need to codegen into something of non-zero length,
otherwise labels get incorrectly merged.  We handled this by emitting a 
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes.  Handle this by emitting a noop.  This
is more gross than it should be because arm/ppc are not fully mc'ized yet.

This fixes rdar://7908505



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102400 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 23:37:21 +00:00
Dale Johannesen
efc3a6348a Add PPC AsmPrinter handling for target-specific form of
DBG_VALUE, and a cautionary comment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102371 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 20:05:01 +00:00
Evan Cheng
962021bc7f - Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 07:38:55 +00:00
Evan Cheng
2dbc8bdfe9 Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 23:51:38 +00:00
Evan Cheng
506049f29f - Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality.
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97628 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 01:44:33 +00:00
Chris Lattner
518bb53485 move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-09 19:54:29 +00:00
Evan Cheng
96dc115ef3 Add two target hooks to determine whether two loads are near and should be scheduled together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-22 03:34:51 +00:00
Dale Johannesen
243a32f96b Remove DEBUG_DECLARE, looks like we don't need it.
Also, DEBUG_VALUE has side effects.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93498 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-15 01:50:44 +00:00
Evan Cheng
7da9ecf967 Add a quick pass to optimize sign / zero extension instructions. For targets where the pre-extension values are available in the subreg of the result of the extension, replace the uses of the pre-extension value with the result + extract_subreg.
For now, this pass is fairly conservative. It only perform the replacement when both the pre- and post- extension values are used in the block. It will miss cases where the post-extension values are live, but not used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93278 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-13 00:30:23 +00:00
Evan Cheng
a5a81d7072 Add TargetInstrInfo::isCoalescableInstr. It returns true if the specified
instruction is copy like where the source and destination registers can
overlap. This is to be used by the coalescable to coalesce the source and
destination registers of instructions like X86::MOVSX64rr32. Apparently
some crazy people believe the coalescer is too simple.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93210 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-12 00:09:37 +00:00
Dale Johannesen
d2035203a0 Add DEBUG_DECLARE. Not used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93040 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-09 01:24:25 +00:00
Dale Johannesen
87563b3937 Add DEBUG_VALUE. Not used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93030 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-08 23:51:25 +00:00
Jakob Stoklund Olesen
d1862037f0 Add comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-07 00:51:04 +00:00
Jakob Stoklund Olesen
30ac0467ce Add Target hook to duplicate machine instructions.
Some instructions refer to unique labels, and so cannot be trivially cloned
with CloneMachineInstr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92873 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-06 23:47:07 +00:00
Bill Wendling
85de1e5bad Whitespace changes, comment clarification. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91274 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-14 06:51:19 +00:00
Dan Gohman
864e2efce2 Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-05 00:44:40 +00:00
David Greene
63be493b52 Remove an unneeded include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90627 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-05 00:03:24 +00:00
David Greene
03c8406fc1 Fix a bad merge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90616 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-04 23:08:02 +00:00