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688 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
fc7bc5889b Move more code around and duplicate AVX patterns: MOVHPS and MOVLPS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138897 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 21:15:32 +00:00
Bruno Cardoso Lopes
06c982d0e0 Move MOVAPS,MOVUPS patterns close to the instructions definition 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138896 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 21:15:29 +00:00
Bruno Cardoso Lopes
453f4954f2 Remove "_Int" forms of MOVUPSmr and MOVAPSmr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 21:15:22 +00:00
Bruno Cardoso Lopes
57d6a5e491 - Move all MOVSS and MOVSD patterns close to their definitions 
- Duplicate some store patterns to their AVX forms!
- Catched a bug while restricting the patterns subtarget, fix it
  and update a testcase to check it properly

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138851 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 03:04:20 +00:00
Bruno Cardoso Lopes
fc646a6b06 Remove unnecessary AVX checks 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138850 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 03:04:14 +00:00
Evan Cheng
0899f5c62d Fix (movhps load) lowering / pattern to match more cases. rdar://10050549 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138848 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 02:05:24 +00:00
Bruno Cardoso Lopes
41dfabb0e3 Move non-intruction patterns to a more appropriate place! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138744 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 17:51:24 +00:00
Craig Topper
8fd13b6de5 Fix disassembling of VCVTSD2SI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138623 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 04:49:29 +00:00
Bruno Cardoso Lopes
f1a264232c Do the same as r138461. Mark VZEROALL as clobbering all YMM registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138592 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 22:23:58 +00:00
Bruno Cardoso Lopes
6292eceea0 Add support for AVX 256-bit version of MOVDDUP! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138588 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 21:40:37 +00:00
Craig Topper
ebc1db0fac Add more missing TB encodings to VEX instructions to allow them to be disassembled. Fixes remainder of PR10678. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138553 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 08:11:01 +00:00
Craig Topper
ea03659d23 Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138551 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 06:57:46 +00:00
Bruno Cardoso Lopes
07b7f672a0 Add support for 256-bit versions of VSHUFPD and VSHUFPS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138546 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 02:58:26 +00:00
Bruno Cardoso Lopes
27831e5e6f Create a section for non-instructions patterns in the beginning of the 
file, and move more code around!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138521 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 23:18:11 +00:00
Bruno Cardoso Lopes
9993499057 Move code around! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138520 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 23:18:09 +00:00
Bruno Cardoso Lopes
de79231468 Organize UNPCK* patterns, also add remaining for AVX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138519 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 23:18:06 +00:00
Bruno Cardoso Lopes
4cf4778ac4 Move remaining MOVDDUP patterns close to MOVDDUP defintion and duplicate 
the missing ones for AVX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138518 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 23:18:04 +00:00
Bruno Cardoso Lopes
4724f25ed6 Organize and tidy up MOVDDUP section. Also update comments! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138517 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 23:18:02 +00:00
Bruno Cardoso Lopes
6140294363 Move MOVHLPS patterns close to MOVHLPS definition, and duplicate the 
pattern for 128-bit AVX mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138516 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 23:17:59 +00:00
Bruno Cardoso Lopes
954d5eabb7 Move all PSHUF* patterns close to the PSHUF* definitions. Also be 
explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Remove old and now wrong comments!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138515 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 23:17:57 +00:00
Bruno Cardoso Lopes
af002d8405 Move all SHUFP* patterns close to the SHUFP* definitions. Also be 
explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Make the mask check more strict, to be
clear it won't be used to match to 256-bit versions!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138514 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 23:17:55 +00:00
Bruno Cardoso Lopes
356e988110 Mark VZEROALL as clobbering all YMM registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138461 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 18:48:33 +00:00
Bruno Cardoso Lopes
d8b7dd5252 Fix a nasty bug where a v4i64 was being wrong emitted with 32-bit 
permutations. Also tidy up some patterns and make them close to their
instruction definition!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138392 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 22:06:37 +00:00
Craig Topper
a534780da0 Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138321 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 04:36:33 +00:00
Bruno Cardoso Lopes
bde9f1b302 Add 128-bit AVX codegen for PCMP* family of integer instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138270 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 20:31:00 +00:00
Craig Topper
e004d941ec Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138034 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 05:28:50 +00:00
Bruno Cardoso Lopes
df01610d6f Re-encoded 128-bit AVX versions of SQRT, RSQRT, RCP have 3 operands 
instead of 2. They were already defined this way in their regular
version, but not for the intrinsics versions (*_Int), and that would work
for assembly emission but not for object code, since a MachineOperand
would be missing. This commit fix PR10697.

Also removed the {VSQRT,VRSQRT,VRCP}r_Int forms and match the intrinsic
via INSERT_SUBREG+EXTRACT_SUBREG patterns. The same couldn't be done for
memory versions because sse_load_f32/sse_load_f64 operand need special
handling and don't work like regular "addr" operands.

There are right now 114 "*_Int" and 98 "Int_*" forms! I'm slowly
removing them as I step through, but hope we can get rid of these
someday, they are really annoying :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138012 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 23:59:21 +00:00
Bruno Cardoso Lopes
24b90e2287 Cleanup vector logical ops in AVX and add use int versions for simple 
v2i64

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137919 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 02:11:34 +00:00
Bruno Cardoso Lopes
0e6d230abd Introduce matching patterns for vbroadcast AVX instruction. The idea is to 
match splats in the form (splat (scalar_to_vector (load ...))) whenever
the load can be folded. All the logic and instruction emission is
working but because of PR8156, there are no ways to match loads, cause
they can never be folded for splats. Thus, the tests are XFAILed, but
I've tested and exercised all the logic using a relaxed version for
checking the foldable loads, as if the bug was already fixed. This
should work out of the box once PR8156 gets fixed since MayFoldLoad will
work as expected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137810 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 02:29:19 +00:00
Bruno Cardoso Lopes
8400bfe9fa While I'm here, remove the "_alt" hacks to a series of INSERT_SUBREG and 
also add the AVX versions of the 128-bit patterns

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137685 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 23:36:51 +00:00
Bruno Cardoso Lopes
1deddbbd56 Reorder declarations of vmovmskp* and also put the necessary AVX 
predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137684 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 23:36:45 +00:00
Bruno Cardoso Lopes
53cae1362d The VPERM2F128 is a AVX instruction which permutes between two 256-bit 
vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137519 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 21:48:26 +00:00
Bruno Cardoso Lopes
fa2f4fd9a2 Move code around and add comments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137518 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 21:48:22 +00:00
Bruno Cardoso Lopes
b02c0ace20 Cleanup: Remove Int_ CVTSS2SI* forms 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137297 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 02:52:36 +00:00
Bruno Cardoso Lopes
6ad251358e The following X86 pattern is incorrect: 
def : Pat<(X86Movss VR128:$src1,
                   (bc_v4i32 (v2i64 (load addr:$src2)))),
          (MOVLPSrm VR128:$src1, addr:$src2)>;
This matches a MOVSS dag with a MOVLPS instruction. However, MOVSS will replace only the low 32 bits of the register, while the MOVLPS instruction will replace the low 64 bits. A testcase is added and illustrates the bug and also modified the one that was already present. Patch by Tanya Lattner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137227 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 17:45:17 +00:00
Bruno Cardoso Lopes
18deb04e9c Add v16i16 and v32i8 store patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137166 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:39:53 +00:00
Bruno Cardoso Lopes
cde4a1abd5 Use fp unpack instructions to unpack int types. Until we have AVX2, this 
is the best we can do for these patterns. This fix PR10554.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137161 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:18:37 +00:00
Bruno Cardoso Lopes
e2406dfd89 Reapply a more appropriate solution than in r137114. AVX supports 
v4f64 = sitofp v4i32. This fix PR10559.
Also add support for v4i32 = fptosi v4f64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137128 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 17:39:13 +00:00
Bruno Cardoso Lopes
2f613c5fff Add support for avx vector fextend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137105 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 03:04:29 +00:00
Bruno Cardoso Lopes
a1dfb63b78 Add AVX versions of 128-bit sitofp and fptosi 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137104 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 03:04:25 +00:00
Bruno Cardoso Lopes
e5118ab7bb Add two patterns to match special vmovss and vmovsd cases. Also fix 
the patterns already there to be more strict regarding the predicate.
This fixes PR10558

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137100 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 01:43:09 +00:00
Bruno Cardoso Lopes
0f0e0a0e58 Make LowerVSETCC aware of AVX types and add patterns to match them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137090 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 00:46:57 +00:00
Bruno Cardoso Lopes
55244ceac4 Add v4f64 -> v2f32 fp_round support. Also add a testcase to exercise 
the legalizer. This commit together with the two previous ones fixes
PR10495.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136654 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-01 21:54:09 +00:00
Bruno Cardoso Lopes
e89c7d4ce3 Add v8i32 and v4i64 vpermil patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136451 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 01:31:07 +00:00
Bruno Cardoso Lopes
9065d4b65f Cleanup PALIGNR handling and remove the old palign pattern fragment. 
Also make PALIGNR masks to don't match 256-bits, which isn't supported
It's also a step to solve PR10489

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136448 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 01:30:59 +00:00
Bruno Cardoso Lopes
93fa4766c2 Add patterns to generate copies for extract_subvector instead of 
using vextractf128. This will reduce the number of issued instruction
for several avx codes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136323 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 01:26:50 +00:00
Bruno Cardoso Lopes
735bccda65 movd/movq write zeros in the high 128-bit part of the vector. Use 
them to match 256-bit scalar_to_vector+zext.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 01:26:46 +00:00
Bruno Cardoso Lopes
a23236c360 Add a few patterns to match allzeros without having to use the fp unit. 
Take advantage that the 128-bit vpxor zeros the higher part and use it.
This also fixes PR10491

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136321 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 01:26:43 +00:00
Bruno Cardoso Lopes
2e64ae4101 Add SINT_TO_FP and FP_TO_SINT support for v8i32 types. Also move 
a convert pattern close to the instruction definition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 01:26:39 +00:00
Kevin Enderby
c37d4bbf1f Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates. 
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
    pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored.  The others remain unchanged.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136287 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 23:01:50 +00:00