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Author SHA1 Message Date
Bill Wendling
ef473bfc44 Print out the name of the function during SSC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104572 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 23:16:04 +00:00
Jakob Stoklund Olesen
33276d95ef Switch SubRegSet to using symbolic SubRegIndices 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 23:03:18 +00:00
Bob Wilson
c21763fd99 Allow Thumb2 MVN instructions to set condition codes. The immediate operand 
version of t2MVN already allowed that, but not the register versions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104570 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 22:41:19 +00:00
Chris Lattner
ec5a0b336a diaggroup categories should take precedence over diag-specific groups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104567 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 21:55:47 +00:00
Jakob Stoklund Olesen
f27462eb29 Lose the dummies 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104564 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 21:47:01 +00:00
Jakob Stoklund Olesen
09bc029865 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data 
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 21:46:58 +00:00
Evan Cheng
3946043a80 Avoid adding duplicate function live-in's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104560 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 21:33:37 +00:00
Dan Gohman
e350690e3b Fix an mmx movd encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104552 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 20:51:08 +00:00
Kevin Enderby
ca956dc0f6 MC/X86: Add aliases for CMOVcc variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104549 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 20:32:23 +00:00
Bob Wilson
d303846e16 Clean up some extra whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104544 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 20:08:34 +00:00
Bob Wilson
bb7ecb2bf5 Thumb2 RSBS instructions were being printed without the 'S' suffix. 
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104531 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 18:44:06 +00:00
Devang Patel
295cdf8b82 Do not emit line number entries for unknown debug values. 
This fixes recent regression in store.exp from gdb testsuite.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104524 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 18:26:49 +00:00
Evan Cheng
c7cf10c97e LR is in GPR, not tGPR even in Thumb1 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 18:00:18 +00:00
Jakob Stoklund Olesen
a1132276e7 Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices are 
never used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104517 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 17:55:38 +00:00
Jakob Stoklund Olesen
d6be874e8c Use SubRegIndex in SystemZ. 
Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104515 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 17:43:01 +00:00
Jakob Stoklund Olesen
fff916a960 SubRegIndex'ize Mips 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104514 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 17:42:58 +00:00
Jakob Stoklund Olesen
59f7199e16 SubRegIndex'ize MSP430 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 17:42:55 +00:00
Jakob Stoklund Olesen
7bb31e3187 Fix a few places that depended on the numeric value of subreg indices. 
Add assertions in places that depend on consecutive indices.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104510 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 17:13:28 +00:00
Jakob Stoklund Olesen
558661d271 Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums 
from ARMRegisterInfo.h

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 16:54:32 +00:00
Jakob Stoklund Olesen
3458e9e4df Rename X86 subregister indices to something shorter. 
Use the tablegen-produced enums.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104493 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 14:48:17 +00:00
Jakob Stoklund Olesen
73ea7bf450 Add the SubRegIndex TableGen class. 
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 14:48:12 +00:00
Nicolas Geoffray
3816c25fdc Encode the Caml frametable by following what the comment says: the number of descriptors 
is first emitted, and StackOffsets are emitted in 16 bits.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104488 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 12:24:11 +00:00
Duncan Sands
4139630212 Apply timeouts and memory limits in more places. In particular, when 
bugpoint does "Running the code generator to test for a crash" this
gets you a crash if llc goes into an infinite loop or uses up vast
amounts of memory.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104485 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 07:49:55 +00:00
Daniel Dunbar
414c0c43d3 llvm-mc: Use EmitIntValue where possible, which makes the API calls from the AsmParser and CodeGen line up better. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104467 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-23 18:36:38 +00:00
Daniel Dunbar
01777ff094 llvm-mc: Use AddBlankLine in asm parser. This makes transliteration match the input much more closely, and also makes the API calls from the AsmParser and CodeGen line up better. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104466 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-23 18:36:34 +00:00
Daniel Dunbar
fdb5a86179 MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104463 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-23 17:44:06 +00:00
Bob Wilson
069e434868 VDUP doesn't support vectors with 64-bit elements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104455 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-23 05:42:31 +00:00
Daniel Dunbar
62e4c671b6 MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: 
addw $0xFFFF, %ax
should match the same as
  addw $-1, %ax
but we used to match it to the longer encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104453 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 21:02:33 +00:00
Daniel Dunbar
54ddf3d9c7 tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104452 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 21:02:29 +00:00
Daniel Dunbar
4c361972fd MC/X86: Add alias for setz, setnz, jz, jnz. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104435 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 06:37:33 +00:00
John Mosby
3422cf05a8 Trivial change to dump() function for SparseBitVector 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104433 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 05:13:17 +00:00
Evan Cheng
2457f2c661 Implement @llvm.returnaddress. rdar://8015977. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 01:47:14 +00:00
Jim Grosbach
5eb1951539 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. 
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104419 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 01:06:18 +00:00
Eric Christopher
1e6d3ac709 This test is darwin only. Make it so(tm). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104418 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 00:55:55 +00:00
Bob Wilson
be751cfe9c Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by 
copying VFP subregs.  This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104415 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 00:23:12 +00:00
Eric Christopher
8116ca5134 Add full bss data support for darwin tls variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104414 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 00:10:22 +00:00
Devang Patel
65eb482e8f Collect variable information during endFunction() instead of beginFunction(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104412 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 00:04:14 +00:00
Eric Christopher
46099f14dc Add a new section and accessor for TLS data. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104411 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 00:00:58 +00:00
Bob Wilson
70fe6643d6 Clean up extra whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104410 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 23:53:55 +00:00
Eric Christopher
e81d010589 Make this LookAheadLimit, not the uninitialized LookAheadLeft. 
Evan please verify!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104408 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 23:40:03 +00:00
Chris Lattner
c2685a9c98 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104404 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 23:16:21 +00:00
Eric Christopher
070c1abbc9 Expand on comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104396 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 23:03:53 +00:00
Kevin Enderby
9d31d79493 Added retl for 32-bit x86 and added retq for 64-bit x86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104394 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 23:01:38 +00:00
Eric Christopher
0df4a80e20 Fix comment and whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104392 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 22:39:11 +00:00
Chris Lattner
299f424f44 expand on the llvm ir bitcode dox. Patch by Peter Housel! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104391 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 22:20:54 +00:00
Evan Cheng
835810bbf8 Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104385 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 21:22:19 +00:00
Eric Christopher
9b00685bb6 Fix section attribute name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104381 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 21:08:52 +00:00
Bob Wilson
78f006acdf Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements 
so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104380 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 21:05:32 +00:00
Evan Cheng
1015ba7018 - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs 
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 20:53:24 +00:00
Jakob Stoklund Olesen
18b2c9d3bf Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction 
reads or writes a register.

This takes partial redefines and undef uses into account.

Don't actually use it yet. That caused miscompiles.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104372 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 20:02:01 +00:00