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6977 Commits

Author SHA1 Message Date
Evan Cheng
caab129cd1 Do not use register as base ptr of pre- and post- inc/dec load / store nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71098 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-06 18:25:01 +00:00
Oscar Fuentes
5dcf50bd03 CMake: Updated lib/CodeGen/CMakeLists.txt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71085 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-06 14:56:40 +00:00
Duncan Sands
a9cad0e7e0 Add generic expansion of SUB when ADD and XOR 
are legal.  Based on a patch by Micah Villmow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71078 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-06 11:29:50 +00:00
Lang Hames
87e3bcab73 Renamed Spiller classes (plus uses and related files) to VirtRegRewriter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71057 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-06 02:36:21 +00:00
Dan Gohman
5412d06e9c If a MachineBasicBlock has multiple ways of reaching another block, 
allow it to have multiple CFG edges to that block. This is needed
to allow MachineBasicBlock::isOnlyReachableByFallthrough to work
correctly. This fixes PR4126.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71018 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-05 21:10:19 +00:00
Evan Cheng
f9a9b51429 Enable stack coloring with regs at -O3. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71010 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-05 20:30:36 +00:00
Chris Lattner
e3f6cea9e9 Do not require variable debug info nodes to have a compile unit. 
For implicit decls like "self" and "_cmd" in ObjC, these decls
should not have a location.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70964 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-05 04:55:56 +00:00
Evan Cheng
bef60d3804 Do not substitute if the new register isn't in the register class of the operand being updated. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70953 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-05 00:46:16 +00:00
Evan Cheng
d923fc621f Move getInstrOperandRegClass from the scheduler to TargetInstrInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70950 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-05 00:30:09 +00:00
Evan Cheng
c3806ea3bc Do forward and backward substitution to eliminate loads and stores when possible. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70937 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-04 23:13:13 +00:00
Chris Lattner
af29a5235d Make DBG_STOPPOINT nodes, and therefore DBG_LABEL labels, get a DebugLoc, so that it 
shows up in -print-machineinstrs.  This doesn't appear to affect anything, but it was
weird for some DBG_LABELs to have DebugLocs but not all of them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70921 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-04 22:10:05 +00:00
Argyrios Kyrtzidis
28f1412c97 Restore a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70900 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-04 19:23:45 +00:00
Mike Stump
fe095f39e7 Restore minor deletion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70892 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-04 18:40:41 +00:00
Evan Cheng
04fa35ab13 Typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70792 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-03 19:10:11 +00:00
Evan Cheng
c781a243a3 In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all. 
VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants.

Not yet enabled. This is part 1. More coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70787 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-03 18:32:42 +00:00
Anton Korobeynikov
9fe9c8ec7d Fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70770 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-03 13:19:57 +00:00
Anton Korobeynikov
813090cf89 Properly handle sdiv / udiv / srem / urem libcalls 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70764 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-03 13:18:16 +00:00
Anton Korobeynikov
c31642f7af Proper name 16 bit libcalls 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70750 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-03 13:14:08 +00:00
Anton Korobeynikov
2f25c2c63f Add libcall expansion for 16 and 128 bit muls 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70749 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-03 13:13:51 +00:00
Argyrios Kyrtzidis
77eaa6880b -Move the DwarfWriter::ValidDebugInfo check to a static DIDescriptor::ValidDebugInfo 
-Create DebugLocs without the need to have a DwarfWriter around


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70682 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-03 08:50:41 +00:00
Bob Wilson
5ee24e54d7 Allow CONCAT_VECTORS nodes to be legal or have custom lowering for some targets. 
Changes to take advantage of this will come later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70560 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-01 17:55:32 +00:00
Bill Wendling
d5a6381195 Simplify more code and add timer stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70539 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-01 08:40:06 +00:00
Bill Wendling
ff86ef33e2 Simplify more code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70537 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-01 08:35:12 +00:00
Bill Wendling
ef956fc784 Simplify some code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70534 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-01 08:32:14 +00:00
Bill Wendling
7fa8162f08 Fix whitespace. It was confusing me. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70533 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-01 08:25:13 +00:00
Evan Cheng
5b16cd2cdd Code clean up. Bye bye PhysRegTracker. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70524 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-01 01:03:49 +00:00
Argyrios Kyrtzidis
a26eae64dd Make DebugLoc independent of DwarfWriter. 
-Replace DebugLocTuple's Source ID with CompileUnit's GlobalVariable*
-Remove DwarfWriter::getOrCreateSourceID
-Make necessary changes for the above (fix callsites, etc.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70520 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-30 23:22:31 +00:00
Jakob Stoklund Olesen
3a155f0e34 Join cross class copies using getCommonSubClass() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70513 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-30 21:24:03 +00:00
Evan Cheng
0490dcb1b7 Add a smarter heuristic to determine when to coalesce a virtual register with a physical one. More specifically, it avoid tying a virtual register in the loop with a physical register defined / used outside the loop. When it determines it's not profitable, it will use the physical register as the allocation preference instead. 
This is *not* turned on by default. Testing indicates this is just as likely to pessimize code. The main issue seems to be allocation preference doesn't work effectively. That will change once I've taught register allocator "swapping".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70503 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-30 18:39:57 +00:00
Jay Foad
4e5ea553d0 Move helper functions for optimizing division by constant into the APInt 
class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70488 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-30 10:15:35 +00:00
Chris Lattner
6c147293d6 fix a regression handling indirect results: these need to be considered 
memory operands otherwise the writebacks get lost when the inline asm 
doesn't otherwise have side effects.  This fixes rdar://6839427, though
clang really shouldn't generate these anymore.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70455 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-30 00:48:50 +00:00
Bill Wendling
98a366d547 Instead of passing in an unsigned value for the optimization level, use an enum, 
which better identifies what the optimization is doing. And is more flexible for
future uses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-29 23:29:43 +00:00
Nate Begeman
ec8eee2d3a Fix infinite recursion in the C++ code which handles movddup by making it unnecessary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70425 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-29 22:47:44 +00:00
Jakob Stoklund Olesen
ce9be2cf5d MachineInstr::isRegTiedTo{Use,Def}Operand can safely be made const. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70408 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-29 20:57:16 +00:00
Nate Begeman
a641575828 Update comment, replace theoretically impossible check with an assert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70391 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-29 18:13:31 +00:00
Evan Cheng
96f3fd9a7f spillPhysRegAroundRegDefsUses() may have invalidated iterators stored in fixed_ IntervalPtrs. Reset them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70378 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-29 07:16:34 +00:00
Nate Begeman
5a5ca1519e Implement review feedback for vector shuffle work. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70372 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-29 05:20:52 +00:00
Sanjiv Gupta
a3518a1d6a Add a public method called getAddressSpace() to the GlobalAddressSDNode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70366 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-29 04:43:24 +00:00
Chris Lattner
672452d5a0 Disable the load-shrinking optimization from looking at 
anything larger than 64-bits, avoiding a crash.  This should
really be fixed to use APInts, though type legalization happens
to help us out and we get good code on the attached testcase at
least.

This fixes rdar://6836460


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70360 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-29 03:45:07 +00:00
Evan Cheng
1c2f6da331 Determine allocation 'preference' with right register class. I haven't seen this changing codegen so no test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70351 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-29 00:42:27 +00:00
Bill Wendling
be8cc2a3de Second attempt: 
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70343 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-29 00:15:41 +00:00
Evan Cheng
8a8a0dfc3b Move getMatchingSuperReg() out of coalescer and into TargetRegisterInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70309 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-28 18:29:27 +00:00
Jakob Stoklund Olesen
08e791fdb3 Don't coalesce a physical register with an incompatible virtual register. 
If the physical register does not belong to the virtual register's regclass,
don't coalesce. The physical register could be an invalid operand for an
instruction using the vreg.

The regclass matching is done after determining the actual subregisters being copied.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70298 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-28 16:34:35 +00:00
Sanjiv Gupta
d3d965714b Initialized arrays can be in any address space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70297 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-28 16:34:20 +00:00
Jakob Stoklund Olesen
fa4677b483 Move getSubRegisterRegClass from ScheduleDagSDNodesEmit.cpp to a TargetRegisterClass method. 
Also make the method non-asserting. It will return NULL when given an invalid subreg index.

The method is needed by an upcoming patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70296 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-28 16:34:09 +00:00
Evan Cheng
30590f5023 Fix PR4034. Bug in LiveInterval::join when it's compacting new valno's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70291 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-28 06:24:09 +00:00
Evan Cheng
e9ccb3a7d4 Fix for PR4051. When 2address pass delete an instruction, update kill info when necessary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70279 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-28 02:12:36 +00:00
Bill Wendling
c69d56f115 r70270 isn't ready yet. Back this out. Sorry for the noise. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70275 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-28 01:04:53 +00:00
Bill Wendling
2e9d5f912a Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to 
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70270 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-28 00:21:31 +00:00
Evan Cheng
c45288e06b Fix PR4076. Correctly create live interval of physical register with two-address update. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70245 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-27 20:42:46 +00:00